Peripheral Logic Research Articles

Scale-CIM: Precision-scalable computing-in-memory for energy-efficient quantized neural networks

Quantized neural networks (QNNs), which perform multiply-accumulate (MAC) operations with low-precision weights or activations, have been widely exploited to reduce energy consumption. QNNs usually have a trade-off between energy consumption and accuracy depending on the quantized precision, so that it is necessary to select an appropriate precision for energy efficiency. Nevertheless, the conventional hardware accelerators such as Google TPU are typically designed and optimized for a specific precision (e.g., 8-bit), which may degrade energy efficiency for other precisions. Though an analog-based computing-in-memory (CIM) technology supporting variable precision has been proposed to improve energy efficiency, its implementation requires extremely large and power-consuming analog-to-digital converters (ADCs).In this paper, we propose Scale-CIM, a precision-scalable CIM architecture which supports MAC operations based on digital computations (not analog computations). Scale-CIM performs binary MAC operations with high parallelism, by executing digital-based multiplication operations in the CIM array and accumulation operations in the peripheral logic. In addition, Scale-CIM supports multi-bit MAC operations without ADCs, based on the binary MAC operations and shift operations depending on the precision. Since Scale-CIM fully utilizes the CIM array for various quantized precisions (not for a specific precision), it achieves high compute-throughput. Consequently, Scale-CIM enables precision-scalable CIM-based MAC operations with high parallelism. Our simulation results show that Scale-CIM achieves 1.5∼15.8 × speedup and reduces system energy consumption by 53.7∼95.7% across different quantized precisions, compared to the state-of-the-art precision-scalable accelerator.

Экспериментальные исследования радиационного воздействия на микросхемы FRAM

The work is devoted to the study of radiation effects on FRAM memory chips. The effects of heavy charged particles entering the microcircuits are considered, the results in static and dynamic modes are analyzed. In statistical mode, the sensitivity of FRAM did not show any dependencies on the data pattern, but showed a relationship with fluence. In dynamic mode, the order of access to memory cells does not affect the sensitivity of memory. The dependences of the consumption current on the radiation dose and the annealing time after irradiation are given. An effects map is shown showing a two-band area sensitive to the laser. According to its relative area, this is the peripheral logic of the device. Studies have confirmed the usefulness of only a few effect maps. This is consistent with the results of tests for exposure to heavy charged particles.

Urban gardens on the edge of city‐making in Metro Manila

AbstractUrban gardens have emerged at the cracks and edges of the densely built environment of Metro Manila, taking on a variety of forms that cultivate a sense of habitability amid harsh urban conditions. The empirical diversity in the spaces, practices and trajectories of urban gardens in the city, however, often exceeds their usual framings either as state‐sponsored projects from above that seek to transform individual dispositions, or as grassroots initiatives from below that result from conscious collective resistance or encroachment. Framing gardens as a locus to understand city‐making amid massive urbanisation, this paper aims to provide a different account of urban gardens by focusing on how they emerge from a certain edginess, characterised by a coming together of various actions, aspirations and relations, and by a mode of practice marked by a distinctive temporality and peripheral logic. Using particular accounts of gardening from across Metro Manila, the paper demonstrates the edginess of urban gardens in terms of four articulations: as interstitial, provisional, transversal and experimental. Making a garden work and maintaining its place in the city entail consolidating relationships between various urban elements that carve spaces of manoeuvre, produce diverse eventualities, and map onto the indeterminate politics of the maybe.

How Buddhist Monks Use Historical Narratives to Delegitimize a Dominant Institutional Logic: The Case of a Korean Buddhist Organizational Field, 1910–1962

Historical narrative studies suggest that history can be strategically manipulated and narrated by current actors to facilitate change. The studies emphasize that history can be used as a source of narratives to serve present purposes. Building on the studies, this research investigates how leaders use history as a set of narratives to delegitimize a dominant logic, thus facilitating institutional change. The empirical context of this study is a Korean Buddhist organizational field during and after Japanese colonization between 1910 and 1962. This context allows to examine how a group of Korean monks with a peripheral logic (meditation logic) proactively used past stories, legends, and myths to delegitimize a dominant logic (service logic). Their narrative strategies are conceptualized in this study as reviving history, stigmatizing history, and invoking leaders from the past. In integrating the findings with the relevant literature, this research aims to contribute to historical narrative and institutional research.

Study, implementation and testing of radiation tolerant design for testability solutions for CMS OT FE ASICs

The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.

An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride (GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules. Recently emerging GaN-based p-channel field-effect transistors (FETs) and monolithic integration techniques enable the implementation of GaN-based complementary logic (CL) circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functionality. In this article, holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems, based on the material limit of GaN and state-of-the-art experimental results. It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform could be as short as sub-nanosecond, which sufficiently satisfies the requirement of power conversion systems typically with operating frequencies less than 10 MHz. With the currently adopted n-FET-based logic gates (e.g., directly coupled FET logic) replaced by CL gates, the power consumption of peripheral logic circuits could be substantially suppressed by more than 103 times, mainly due to the elimination of the pronounced static power loss. Consequently, the energy efficiency of the entire system could be substantially improved.

Centrality and compatibility of institutional logics when introducing value-based reimbursement.

Using financial incentives has been criticised for putting too much focus on things that can be measured. Value-based reimbursement may better align professional values with financial incentives. However, professional values may differ between actor groups. In this article, the authors identify institutional logics within healthcare-providing organisations. Further, the authors analyse how the centrality and compatibility of the identified logics affect the institutionalisation of external demands. 41 semi-structured interviews were conducted with representatives from healthcare providers within spine surgery in Sweden, where a value-based reimbursement programme was introduced. Data were analysed using thematic content analysis with an abductive approach, and a conceptual framework based on neo-institutional theory. After the introduction of the value-based reimbursement programme, the centrality and compatibility of the institutional logics within healthcare-providing organisations changed. The logic of spine surgeons was dominating whereas physiotherapists struggled to motivate a higher cost for high quality physiotherapy. The institutional logic of nurses was aligned with spine surgeons, however as a peripheral logic facilitating spine surgery. To attain holistic and interdisciplinary healthcare, dominating institutional logics within healthcare-providing organisations need to allow peripheral institutional logics to attain a higher centrality for higher compatibility. Thus, allowing other occupations to take responsibility for quality and attain the feeling of professional pride. Interviewing spine surgeons, physiotherapists, nurses, managers and administrators allows us to deepen the understanding of micro-level behaviour as a reaction (or lack thereof) to macro-level decisions.

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity.

In modern systems, DRAM-based main memory is signi?cantly slower than the processor.Consequently, processors spend a long time waiting to access data from main memory, makingthe long main memory access latency one of the most critical bottlenecks to achieving highsystem performance. Unfortunately, the latency of DRAM has remained almost constant inthe past decade. This is mainly because DRAM has been optimized for cost-per-bit, ratherthan access latency. As a result, DRAM latency is not reducing with technology scaling, andcontinues to be an important performance bottleneck in modern and future systems.This dissertation seeks to achieve low latency DRAM-based memory systems at low costin three major directions. The key idea of these three major directions is to enable and ex-ploit latency heterogeneity in DRAM architecture. First, based on the observation that longbitlines in DRAM are one of the dominant sources of DRAM latency, we propose a newDRAM architecture, Tiered-Latency DRAM (TL-DRAM), which divides the long bitline intotwo shorter segments using an isolation transistor, allowing one segment to be accessed withreduced latency. Second, we propose a ?ne-grained DRAM latency reduction mechanism,Adaptive-Latency DRAM, which optimizes DRAM latency for the common operating conditions for individual DRAM module. We observe that DRAM manufacturers incorporate a very large timing margin as a provision against the worst-case operating conditions, whichis accessing the slowest cell across all DRAM products with the worst latency at the highesttemperature, even though such a slowest cell and such an operating condition are rare. Ourmechanism dynamically optimizes DRAM latency to the current operating condition of theaccessed DRAM module, thereby reliably improving system performance. Third, we observethat cells closer to the peripheral logic can be much faster than cells farther from the peripherallogic (a phenomenon we call architectural variation). Based on this observation, we propose anew technique, Architectural-Variation-Aware DRAM (AVA-DRAM), which reduces DRAMlatency at low cost, by pro?ling and identifying only the inherently slower regions in DRAMto dynamically determine the lowest latency DRAM can operate at without causing failures.This dissertation provides a detailed analysis of DRAM latency by using both circuit-levelsimulation with a detailed DRAM model and FPGA-based pro?ling of real DRAM modules.Our latency analysis shows that our low latency DRAM mechanisms enable significant latencyreductions, leading to large improvement in both system performance and energy e?fficiencyacross a variety of workloads in our evaluated systems, while ensuring reliable DRAM operation.

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology

Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (217) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5σ of variation with Monte Carlo simulations.

Losing the Activist Spirit: Mission Drift and Institutional Logics Vulnerability

In this paper we examine how a hybrid organization struggles, and eventually fails, to balance institutional logics in order to avoid mission drift. We explore this in the context of ITCP-FGV (Technological Incubator of Popular Cooperatives) an organization within a private Brazilian business school based on solidarity economy ideology. Our findings show that three mechanisms – shifting demographics, financial sources, and institutional logics vulnerability – have a great impact on mission drift. We suggest institutional logics are more vulnerable (and thus become a peripheral logic or even disappear) if the logic a) is under-represented from within the organization, b) has an insufficient degree of institutionalization, c) lacks institutional logic referents at higher levels and, d) appears in an organization at the field’s periphery and is thus less susceptible to the field’s normative influence. Moreover, we propose that spaces of reflexivity are a crucial instrument to avoid mission drift, since they ...

Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy

The influence of post-deposition annealing (PDA) temperature condition on charge distribution behavior of HfO2 thin films was systematically investigated by various-temperature Kelvin probe force microscopy technology. Contact potential difference profiles demonstrated that charge storage capability shrinks with decreasing annealing temperature from 1,000 to 500 °C and lower. Compared to 1,000 °C PDA, it was found that 500 °C PDA causes deeper effective trap energy level, suppresses lateral charge spreading, and improves the retention characteristics. It is concluded that low-temperature PDA can be adopted in 3D HfO2-based charge trap flash memory to improve the thermal treatment compatibility of the bottom peripheral logic and upper memory arrays.

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

One way to organize 3-D memories is cell arrays stacked on logic where the upper die layers contain the cell arrays and the bottom layer implements the peripheral logic. A new degree of freedom exists when constructing 3-D memories, which is that the order of the die in the stack can be selected. This paper proposes a new idea that exploits this additional degree of freedom to reduce the cost of yield enhancement. In the proposed approach, the cell array die with the most defective cells is placed in the lowest layer, followed by the next most defective cells in the second lowest layer, and so forth finishing with the die with the fewest defective cells on the top layer. The bottommost layer (peripheral logic) is designed such that it costs less to tolerate the defects on the lower layers than it does on higher layers of the cell arrays. This is done by limiting the domain over which some spares can be used thereby reducing the number of fuses needed for configuring the spare. Results show that the asymmetric repair capability created by fine tuning the domain of spares in a 3-D integrated circuit allows yield enhancement at a lower cost in terms of number of spares and fuses.

Implementation of Fuzzy Self-Tuning PID and Feed-Forward Design for High-Performance Motion Control System

The existing conventional motion controller does not perform well in the presence of nonlinear properties, uncertain factors, and servo lag phenomena of industrial actuators. Hence, a feasible and effective fuzzy self-tuning proportional integral derivative (PID) and feed-forward control scheme is introduced to overcome these problems. In this design, a fuzzy tuner is used to tune the PID parameters resulting in the rejection of the disturbance, which achieves better performance. Then, both velocity and acceleration feed-forward units are added to considerably reduce the tracking error due to servo lag. To verify the capability and effectiveness of the proposed control scheme, the hardware configuration includes digital signal processing (DSP) which plays the main role, dual-port RAM (DPRAM) to guarantee rapid and reliable communication with the host, field-programmable gate array (FPGA) to handle the task of the address decoder and receive the feed-back encoder signal, and several peripheral logic circuits. The results from the experiments show that the proposed motion controller has a smooth profile, with high tracking precision and real-time performance, which are applicable in various manufacturing fields.

A Low-Noise High-Dynamic-Range 17-b 1.3-Megapixel 30-fps CMOS Image Sensor With Column-Parallel Two-Stage Folding-Integration/Cyclic ADC

A 1.3-megapixel CMOS image sensor (CIS) with digital correlated double sampling and 17-b column-parallel two-stage folding-integration/cyclic analog-to-digital converters (ADCs) is developed. The image sensor has 0.021-erms- vertical fixed pattern noise, 1.2-erms- pixel temporal noise, and 85.0-dB dynamic range using 32 samplings in the folding-integration ADC mode. Despite the large number of samplings (32 times), the prototype image sensor is demonstrated at the video rate operation of 30 Hz by the new architecture of the proposed ADCs and the high-performance peripheral logic (or digital) parts using low-voltage differential signaling circuit. The developed 17-b CIS has no visible quantization noise at very low light level of 0.01 lx because of high grayscale resolution where 1LSB = 0.1-. The implemented CIS using 0.18- μm technology has the sensitivity of 20 V/lx ·s and the pixel conversion gain of 82 μV/e-.

Design and Realization of High-Speed and Real-Time Signal Processing System Based on FPGA

We usually adopt DSP and ARM to perform signal collection and processing. However, functions of DSP and ARM largely depend on the software. Parameter modulation of the software must account for sampling time partly. Moreover, software can not control complex peripheral logic circuit very well. The above problems render DSP and ARM containing big flaws in high-speed data collection and processing. Field-programmable Gate Array (FPGA) possesses the characteristics of timeliness, controllability and rapid processing speed. The paper designed a new circuit based on FPGA to obtain high-speed signal, and utilized FFT IP core in FPGA to perform spectral analysis with the help of digital signals from the circuit. The paper introduced the design based on FPGA and verified that it possesses good performance according to actual experiments.

A cultura escolar católica da cátedra de Sociologia nos primórdios da Universidade Federal do Rio Grande do Sul

Os estudos sobre a institucionalização da Sociologia no Brasil dedicaram-se aos casos centrais como São Paulo e Rio de Janeiro, em suas devidas diferenças. Entretanto, o padrão de institucionalização da Sociologia no Brasil foi a variante regional. Nesses contextos, seus precursores foram representantes das elites que definiram e reproduziram as problemáticas sociais consideradas legítimas. Essa lógica periférica da Sociologia teve no Rio Grande do Sul um caso emblemático. Refere-se ao fato de que a Cátedra de Sociologia da Universidade Federal do Rio Grande do Sul (UFRGS) foi consagrada a um representante da geração católica: Laudelino Medeiros. Desse modo, demonstra-se nesse artigo como Medeiros redefiniu seus referenciais católicos dominantes para a Sociologia que ministrou. Contou-se, para tanto, com várias fontes, privilegiando-se aquelas referentes à metodologia levantada da cultura escolar.

A novel prototype of auxiliary edge resonant bridge leg link snubber‐assisted soft‐switching sine‐wave PWM inverter

AbstractThis paper proposes a new circuit topology of the three‐phase soft‐switching PWM inverter and PFC converter using IGBT power modules, which has the improved active auxiliary switch and edge resonant bridge leg‐commutation‐link soft‐switching snubber circuit with pulse current regenerative feedback loop as compared with the typical auxiliary resonant pole snubber discussed previously. This three‐phase soft‐switching PWM double converter is more suitable and acceptable for a large‐capacity uninterruptible power supply, PFC converter, utility‐interactive bidirectional converter, and so forth. In this paper, the soft‐switching operation and optimum circuit design of the novel type active auxiliary edge resonant bridge leg commutation link snubber treated here are described for high‐power applications. Both the main active power switches and the auxiliary active power switches achieve soft switching under the principles of ZVS or ZCS in this three‐phase inverter switching. This three‐phase soft‐switching commutation scheme can effectively minimize the switching surge‐related electromagnetic noise and the switching power losses of the power semiconductor devices; IGBTs and modules used here. This three‐phase inverter and rectifier coupled double converter system does not need any sensing circuit and its peripheral logic control circuits to detect the voltage or the current and does not require any unwanted chemical electrolytic capacitor to make the neutral point of the DC power supply voltage source. The performances of this power conditioner are proved on the basis of the experimental and simulation results. Because the power semiconductor switches (IGBT module packages) have a trade‐off relation in the switching fall time and tail current interval characteristics as well as the conductive saturation voltage characteristics, this three‐phase soft‐switching PWM double converter can improve actual efficiency in the output power ranges with a trench gate controlled MOS power semiconductor device which is much improved regarding low saturation voltage. The effectiveness of this is verified from a practical point of view. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 155(4): 64–76, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20207

SOFT ERRORS IN COMMERCIAL INTEGRATED CIRCUITS

The once-ephemeral soft error has recently caused considerable concern for manufacturers of advanced silicon technology as this phenomenon now has the potential for inducing the highest failure rate of all other reliability mechanisms combined. We briefly review the three radiation mechanisms responsible for causing soft errors in commercial electronics and the basic physical mechanism by which ionizing radiation can produce a soft error. We then focus on the soft error sensitivity trends in commercial DRAM, SRAM, and peripheral logic devices as a function of technology scaling and discuss some of the solutions used for mitigating the impact of soft errors in high reliability systems.

A Novel Prototype of Auxiliary Edge Resonant Bridge Leg-Link Snubber-Assisted Soft-Switching Sinewave PWM Inverter

This paper proposes a new circuit topology of the three-phase soft switching PWM inverter and PFC converter using IGBT power modules, which has the improved active auxiliary switch and edge resonant bridge leg-commutation-link soft-switching snubber circuit with pulse current regenerative feedback loop as compared with the typical auxiliary resonant pole snubber discussed previously. This three-phase soft switching PWM double converter is more suitable and acceptable for a large capacity uninterruptible power supply, PFC converter, utility-interactive bi-directional converter and so forth. In this paper, the soft switching operation and optimum circuit design of the novel type active auxiliary edge resonant bridge leg commutation link snubber treated here are described for high power applications. Both the main active power switches and the auxiliary active power switches achieve soft switching under the principles of ZVS or ZCS in this three-phase inverter switching. This three-phase soft switching commutation scheme can effectively minimize the switching surge related electromagnetic noise and the switching power losses of the power semiconductor devices; IGBTs and modules used here. This three-phase inverter and rectifier coupled double converter system does not need any sensing circuit and its peripheral logic control circuits to detect the voltage or the current and does not require any unwanted chemical electrolytic capacitor to make the neutral point of the DC power supply voltage source. The performances of this power conditioner are proved on the basis of the experimental and simulation results. Because the power semiconductor switches (IGBT module packages) have the relation of the trade-off in the switching fall time and tail current interval characteristics as well as the conductive saturation voltage characteristics, this three-phase soft-switching PWM double converter can perform to improve actual efficiency in the output power ranges with a trench gate controlled MOS power semiconductor devices which is much more improved to the low saturation voltage. The effectiveness of this is verified from a practical point of view.