Peripheral Logic Research Articles

Trends in low-voltage embedded-RAM technology

First, trends in the gate-oxide thickness of MOSFET for DRAM and MPU are discussed to clarify the strong need for low-voltage operation of embedded RAMs. Then, modern peripheral logic circuits for reducing leakage currents and DRAM/SRAM cells to cope with the ever-decreasing signal charges are described. Finally, needs for developments of subthreshold-current reduction circuits for use in active mode, memory-rich SoC architectures, and gain cells and non-volatile cells are emphasized.

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q/sub s/) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-/spl mu/m CMOS process. The chip size is 7.9/spl times/16.7 mm/sup 2/ and cell size is 1.35/spl times/2.8 /spl mu/m/sup 2/.

A 1 kbit Josephson random access memory using variable threshold cells

The variable-thresholds cell has the advantages of simple structure and small size. In order to achieve nondestructive readout, rewriting has been carried out with peripheral circuits consisting of latching logic gates without any superconducting loop. OR-INVERT address decoders powered by a two-phase supply are used instead of the AND decoders of previous Josephson RAM chips. The 1 kbit (256*4 bit) RAM chip was fabricated using an Nb/Al-oxide/Nb tunnel junction technology with a 3 mu m design rule. Experimental results show no failure in the 1028 logic gates of the peripheral circuits, and only a 2% bit failure in the cell plane of 1024 bits. Total power dissipation of the chip, including peripheral logic circuits, is 1.9 mW. A preliminary measurement yields an access time of about 500 ps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis strategy for internal measurements on VLSI devices

In the VLSI product development, design as well as process related failures may be regarded as the cause for systematic malfunctions on the chip, concealing additional statistical defects and weaknesses. In an extreme case — as will be reported here — the storage function of a DRAM was crippled by serious faults in the peripheral logic. Consequently no experience was gained with respect to the storage cell area, in which the highest level of integration is achieved. This has very severe consequences for the learning curve, which normally must be very steep due to enormous market pressure. Considering the extreme complexity of today's integrated circuits (submicron regime) this steep condition is however hard to maintain. The present paper outlines an analysis strategy of how these difficulties can be overcome if the conditions are favorable, and thus stay on the learning curve.

High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals

This paper describes the high-speed time division switch employed in a 32-Mbit/s bearer signal communications system. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large channel capacity time division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time division switches necessary for such services as TV and high-definition TV communications.

Newly structured 512 Mbit/s high-speed time-division switch

The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.

Global and Modular Two's Complement Cellular Array Multipliers

Two new families of LSI iterative logic arrays are proposed to perform two's complement multiplication based on the Baugh–Wooley algorithm [2]. The global approach is faster and attractive for LSI but limited in size due to current monolithic and packaging technology. The modular approach is better suited to realizing arbitrarily large array multipliers at only slight decrease in speed. The proposed additive multiply modules can be externally programmed by hardwiring to multiply binary numbers in either two's complement or unsigned format. No peripheral logic circuits such as Wallace trees or complementers are needed in constructing the proposed modular multiplication networks. Speed analysis, hardware complexity, packaging, and application requirements of the proposed array multipliers are also provided.

Self-contained charge-coupled split-electrode filters using a novel sensing technique

Self-contained single-chip charge-coupled split-electrode filters with 55 taps and a novel channel structure have been built with a double-level polysilicon NMOS process. Operating at a sample rate of 32 kHz, these devices provide a low-pass filter function with a passband from 0 to 3.2 kHz and a stopband above 4 kHz. The image charge on the sense electrodes is detected with a novel sensing circuit employing two on-chip operational amplifiers, one of which suppresses the common-mode signal on the two sense buses while the other one integrates the difference signal. In addition, the chips carry antialiasing prefilters, a correlated double sample-and-hold circuit to minimize reset noise and to restore the output signal, and all the necessary peripheral logic and biasing circuitry so that the devices can be operated from a single master clock and two power supplies of +12 and -5 V, respectively.

Programmable Cellular arrays†

Different cellular cascades and arrays for realizing arbitrary logical functions as well as special-purpose arrays for parallel arithmetical operations are reviewed. A 4 X 3 cellular array is designed using a basic cell which realizes all the Boolean functions of its two input variables and also includes a flip-flop. The individual cells in the array can be selected and programmed from outside the package for different logic functions. The necessary peripheral logic for accomplishing this is suggested. A large variety of logical subsystems like full adders, code converters, shift registers, etc. are synthesized using these cellular arrays.

Some Simple Self-Synchronizing Digital Data Scramblers

Two types of self-synchronizing digital data scramblers and descramblers are introduced and examined. The descramblers recover synchronization quickly after the insertion or deletion of channel bits, and they are relatively insensitive to channel errors. The scramblers act to increase the period of periodic data sequences, and the periodic channel sequences produced have approximately half as many transitions in one period as there are bits in a period. These circuits find application in common carrier systems where short-period data sequences produce high-level tones in the transmission band and, as a consequence, interchannel interference. And they have application when receiver clocks derive synchronization from transitions in the channel signal. A number of variations and modifications of the scramblers which affect their cost and size are considered. The scramblers and descramblers are similar in construction and consist of linear sequential filters with either feed-forward or feedback paths, counters, storage elements and peripheral logic. The counters, storage elements and peripheral logic monitor the channel sequence but react infrequently so that the scramblers and descramblers behave principally as linear sequential filters.