Performance Of Power Amplifier Research Articles

A Reconfigurable Hybrid Series/Parallel Doherty Power Amplifier With Antenna VSWR Resilient Performance for MIMO Arrays

Antenna load impedance variations typically cause significant power amplifier (PA) performance degradation, including output power, large-signal linearity, and peak/average PA efficiency, which are especially critical for modern millimeter-wave (mm-Wave) communications with spectrally efficient complex modulations. To address this problem, we propose a reconfigurable hybrid series/parallel Doherty PA with a 90°coupler-based active load modulation network. By reconfiguring the series/parallel Doherty operation modes, the strengths of the Main/Auxiliary PAs, and their relative phase, linear output power (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ), as well as peak output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) and energy efficiency (PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> and PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of the PA can be largely restored under full-span 360° antenna impedance variations. The theoretical analysis and design guidelines are both presented in this article. As a proof of concept, a 39-GHz reconfigurable hybrid series/parallel Doherty PA is fabricated in the Global Foundries 45-nm RF CMOS silicon on insulator (SOI) process with a 2-V PA supply and 1-V driver supply. At 39 GHz, the PA achieves a 33.3% peak power-added efficiency (PAE) at 20.8-dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> and 32.2% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> at 20.2-dBm OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> at a nominal 50-Ω load. The reconfigured PA demonstrates an 18.5-19.12-dBm OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> with a high PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> of 20.6%-25.3% at 3:1 antenna voltage standing wave ratio (VSWR) over 360° angles. The PA achieves an rms error vector magnitude (EVM) of -23.6 dB/-22.8 dB/-23.1 dB at an average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 13.8 dBm/12.2 dBm/11.5 dBm with 100 MSym/S/500 MSym/S/1 GSym/S single-carrier 64-quadratic amplitude modulation (QAM) signal, respectively, at a nominal load of 50 Ω. A greater-than 11.2-dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> is achieved at an rms EVM of -24 dB under a full-span 3:1 antenna VSWR with a 100-MSym/S 64-QAM signal.

A novel two‐dimensional crest factor reduction method based on concurrent output capacity of power amplifiers

AbstractA novel two‐dimensional crest factor reduction (2D‐CFR) is proposed to improve the dual‐band concurrent performance of power amplifiers (PAs). The concurrent performance of target PA can be improved significantly when the power for peak detection conforms to the concurrent characteristic. Peak detection and clipping operation are presented based on concurrent output capacity of PAs, which can be efficiently described by introducing two design parameters. Measured results show that the drain efficiency is improved from 34.2% to 36.6% with the proposed 2D‐CFR when compared with the conventional 2D‐CFR while maintaining similar error vector magnitude and ACPRs, which indicates a significant performance improvement.

An X-Band Class-J Power Amplifier With Active Load Modulation to Boost Drain Efficiency

In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $\alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $\phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $\alpha $ and $\phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $\mu \text{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

The requirement of low-power analog circuits has been raised in recent years due to the strict limitation of power consumption in modern applications. Therefore, the trend in analog circuit design has been changed such that they are able to meet the required specifications with lower power dissipation. Design of low power operational transconductance amplifiers, which are the main building blocks in many analog applications, has been more pronounced to keep the power dissipation below certain levels. In this concern, this study presents a low power, high-performing bulk-driven 3 stages CMOS OTA in a 130 nm standard CMOS technology. The proposed circuit leverages the bulk-driven architecture at the input stage; thus it can operate under sub 1-V. The design process of the proposed OTA is explained in detail and the results are validated via post-layout simulations. The proposed OTA is powered by ±0.45 V symmetric voltage sources, where the power consumption is around 27 μW. The area overhead is only 0.0017μm2. The open-loop gain, unity gain frequency, and the phase margin are 73.24 dB, 5.167MHz, and 78o, respectively. To demonstrate the performance of the proposed circuit, a comparison is made with other circuits published in the last five years considering the well-known figures of merit (FOMs). Comparison results indicate that the proposed solution outperforms the other circuits for small-signal operation while it is the runner-up for large-signal operation.

Comparative Analysis of the Effect of Loaded Quality Factor, Technology Node and Operating Frequency on Various Class E Power Amplifier Topologies

This paper aims to explore and compare the dependence of power amplifier performance parameters on the loaded quality factor of the resonant circuit, the technology node used and the operating frequency for different variants of the class E power amplifier. In spite of the fact that the circuit parameter variations of the basic class E amplifier are present in the literature, there is a lack of comparative analysis with respect to other class E power amplifiers based on diverse tuned load networks. Moreover, the effects of these three parameters are rarely discussed. The comparative analysis helps the designers to narrow down the selection of a power amplifier to be used for a particular application. This study is focused on the use of class E power amplifiers in biomedical implants at the Medical Implant Communication Service band and Industrial Scientific and Medical band. It is observed that the power added efficiency and the power gain have an inverse dependence on the loaded quality factor, frequency and the technology node while the output power depends directly on these parameters.

Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications

This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range of DeFinFET options. The same is then compared, in terms of radio frequency (RF)-power amplifier (PA) performance, dc-dc conversion efficiency, electrostatic discharge (ESD) robustness, and hot carrier immunity (HCI) reliability, with other HV alternatives in FinFET nodes and its planar counterpart, that is drain-extended MOS (DeMOS).

Optically pumped HBr master oscillator power amplifier operating in the mid-infrared region

An optically end-pumped HBr master oscillator power amplifier (MOPA) has been demonstrated for what we believe is the first time. It produced up to 10.3 mJ per pulse at 4.20 and 4.34 µm when pumped with a single-frequency Ho:YLF MOPA system at a pulse repetition frequency of 50 Hz. Wavelength selection with the use of an intracavity C O 2 absorption cell was also demonstrated, forcing the oscillator to emit at 3.89, 4.13, and 4.16 µm simultaneously, with a maximum output energy of 6.5 mJ per pulse after amplification.

Input-Harmonic-Controlled Broadband Continuous Class-F Power Amplifiers for Sub-6-GHz 5G Applications

A comprehensive analysis is presented for investigating the effects of input nonlinearity on performance and broadband design of continuous-mode class-F power amplifiers (PAs). New time-domain waveforms are derived considering input and output harmonic terminations for continuous-mode class-F operation. The derived design equations show that the typical fundamental load design space of a continuous class-F PA must be reengineered in the presence of second-harmonic input nonlinearity to new design space in order to achieve optimum class-F PA performance versus varying second-harmonic load impedance. For the practical validation, the impacts of input nonlinearity on the performance of continuous-mode class-F PAs are first confirmed with pulsed vector load–pull (VLP) measurements on a low-power GaN 2-mm device. Second, a broadband high-power GaN 24-mm part is designed following the proposed theory with in-package input second-harmonic terminations targeting 1.75–2.3-GHz frequency band for the sub-6 GHz 5G high-power applications. Efficiency higher than 65% with peak power more than 53.2 dBm was maintained over the target frequency band, with excellent flatness. Third, a Doherty PA is implemented based on the designed GaN 24-mm part to evaluate the broadband performance with modulated stimuli. Using a multicarrier signal having an instantaneous bandwidth of 395 MHz, the average drain efficiency of the Doherty PA at 8-dB output back-off is higher than 44%, and the linearized adjacent channel power ratio (ACPR) is better than −52 dBc.

A Sandwiched-Slab-Transformer-Based SiGe Power Amplifier Operating at W- and D-Bands

In this letter, a 75.1–151.4-GHz silicon power amplifier (PA) is devised with the help of sandwiched slab transformer, which is proposed to increase the tuning ranges of coupling coefficient, quality factor, and conductivity. Being compact in size and simple in implementation enables it to be well-applied in multiple-way power combination. Based on this device, the fabricated PA in the 130-nm silicon germanium (SiGe) process demonstrates more than 14.1-dB gain at full $W$ -band and 77% of the $D$ -band. From 75 to 117.7 GHz, its measured $P_{\mathrm {sat}}$ is all above 16.8 dBm, while its peak point is 19.8 dBm at 100 GHz with 8.8% PAE.

Analysis and design of a novel concurrent Class B/J continuum power amplifier

In this paper, a novel concurrent Class B/J continuum mode is presented based on waveform shaping of current and voltage. The behavior characteristics and performances of power amplifiers (PAs) in concurrent dual-band mode are investigated in detail. According to the analysis of proposed concurrent mode, the optimal load impedances at fundamental, harmonic and intermodulation (IM) frequencies are related to the magnitude ratio of the two carriers. Comparing with concurrent Class-B mode, two parameters α, β can be configured independently in the proposed concurrent mode, which provides more freedom and flexibility for design without output power and drain efficiency degradation. In order to verify the proposed theory, a 1.9/2.35 GHz dual-band power amplifier based on proposed concurrent mode is designed, fabricated and measured. Experimental results show that when the PA is driven by two 10 MHz LTE signals concurrently with total 9.2 dB peak-to-average power ratio (PAPR), the total average power is 36.0 dBm with 40.6% drain efficiency, which indicates a good concurrent performance.

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

Novel Drain-Connected Field Plate GaN HEMT Designs for Improved V BD–R ON Tradeoff and RF PA Performance

TCAD studies are performed to develop physical insights into the breakdown behavior of drain-connected field plate-based GaN HEMTs. Using the developed insights, to mitigate the performance bottleneck caused by the lateral drain-connected field plate design, we have proposed novel vertical-field-plate designs. The proposed designs alleviate the channel electric field by uniformly distributing it vertically into the GaN buffer region. As a result, the proposed vertical and dual-field-plate design offer ${2} \times $ and ${3} \times $ improvements in breakdown voltage, respectively, compared with the design without field plate. Similarly, compared with a design with a lateral field plate, a 50% improvement in the breakdown voltage was seen with dual-field-plate architecture. RF power amplifier (PA) performance extracted using load-pull simulations demonstrates an improved RF PA linearity at higher drain bias, improved output power, efficiency, and PA gain for HEMTs with dual- and vertical-field-plate designs.

Low heat-effect side-pumping gain module with evenly Gaussian to flat-top fluorescence distribution

A diode side-pumping gain module designed and optimized to provide even fluorescence distribution is demonstrated. Heat effects of lasers using the optimized module are considerably lower comparing with that using the unoptimized commercial module. In the master oscillator power amplifier operation, the output pulse energy reaches 4.4 mJ at the repetition rate of 1 kHz with the pulse width of 900 ps; and the thermal focal length is ~50% longer than that of the unoptimized module under the same condition.

Envelope emulation

Researchers from the UK present a novel characterisation system that is capable of emulating a complete envelope tracking power amplifier (ET-PA) environment around a microwave power transistor. The system achieves this by using modulated impedance synthesis and a dynamic supply voltage generation, as well as industry-standard modulated signals and digital pre-distortion. The authors believe that the system will be of use to designers of ET-PAs, allowing more complete investigation of the performance of ET-PAs in realistic modulated and load impedance conditions. As communication systems evolve to transmit ever-larger volumes of data, including the ongoing roll-out of 5G worldwide, we will need to develop more advanced modulation schemes to satisfy the rampant growth and to improve spectral efficiency. Whilst new modulation schemes offer higher data throughput levels, they are characterised by high peak-to-average power ratios (PAPRs). Power amplifiers (PA) are the major power consumer in mobile communication systems, and thus several power amplifier architectures have been proposed to improve average PA efficiency, including the Doherty PA and envelope tracking (ET). Authors (right to left) Sattam Alsahali, Alexander Alex,Dr. Jonathan Lees and Dr. Peng Chen. Set-up of the present work. Average PAE for 28 V fixed bias (blue solid contours) and for ET (green dotted contours). ET works by rapidly changing the supply voltage of the PA in response to the input signal, providing low supply voltage for low powers and vice versa. Whilst ET presents itself as a strong candidate for a wide range of applications due to its potential to support both multimode and multiband operations, the design of the ET-PA presents an array of challenges relating to optimisation of and interaction between involved sub-systems, in particular the radiofrequency (RF) potential of the ET-PA. Characterising the performance of a radiofrequency power amplifier (RFPA) and optimising its performance as early as possible within the ET environment is highly desirable. Load-pull, the colloquial term for the process of systematically varying impedance presented to a device under test, is a robust approach commonly utilised at the beginning of the design phase of an RFPA to characterise the device's performance at fundamental and harmonic frequencies, typically in terms of output power, efficiency, gain and linearity. The work presented by Alsahali et al. is the first work that combines a fast, modulated load-pull system (known as the Mesuro RAPID system) and digital pre-distortion, producing a powerful ET characterisation bench. Achieving this ET characterisation bench wasn't easy, the team had to combine and synchronise a number of different systems. In particular, the efficiency measurement and the time alignment between the RF signal and the tracking signal were especially challenging to characterise. Despite the challenges, the team's Letter shows that they ultimately succeeded in pulling together myriad subsystems to produce a highly useful package. The authors hope that their proposed system will be useful for the future design of ET-PAs by providing a powerful emulation tool. This first example only allows for fundamental load pull, in order to fully investigate the potential of the new measurement architecture, the ability to incorporate harmonics, specifically the 2nd and 3rd harmonics (significant in realising highly efficient PA modes of operation), will be highly beneficial. In addition, it was found that the modulation bandwidth of the Mesuro RAPID load-pull system is limited to 40 MHz. A 5G system will require at least 100 MHz to fully characterise the nonlinearity of RFPAs, which requires at least five times the modulation bandwidth. The group has already begun working on these bandwidth enhancements - watch this (ever expanding) space.

Power‐efficient full‐duplex K/Ka‐band phased array front‐end

This study presents the first monolithically integrated full-duplex front-end for K/Ka satellite communication phased arrays. A 0.25 μm SiGe:C BiCMOS process was used to develop the integrated circuit. The receive and transmit channels are united into a common port through a novel duplexer. For each RF channel, the bias currents, the active channels and the power amplifier operation mode can be controlled through a serial bus. Amplitude and phase control are provided with fine granularity (65,536 states). In transmit mode, each channel provides 37.3 dB of gain with 12.9 dBm output power at 1-dB compression. In receive mode, 33.7 dB gain is measured with a noise figure of 3.2 dB. The amplitude/phase root-mean-square errors within the transmit (29.5–30.8 GHz) and receive (19.7–21 GHz) bands are below 0.7 dB/ 6.4 ° and 0.26 dB/ 1.1 ° , respectively. The chip occupies 1.64 × 3.5 m m 2 and it consumes 81 and 15.5 mW per transmit and receive channels, respectively. The use of a Doherty power amplifier with a novel dynamic adaptive bias circuit led to a 31% reduction of the total dc array power consumption.

INVESTIGATION OF THE DESIGN OF MEASURING EQUIPMENT INFLUENCE ON THE OPERATION OF A SOLID-STATE POWER AMPLIFIER

The measuring equipment influences the operation of solid-state power amplifier by inducing parasitic components in the operating frequency range. Operation of differential amplifier and a low noise amplifier were studied. The measuring equipment for these devices was developed and the issue stated was experimentally solved.

The peak windowing for PAPR reduction in software defined radio base stations

The utilization of the techniques for Peak to Average Power Ratio (PAPR) reduction makes the wireless infrastructure conform to rigorous telecommunication standard specifications (error vector magnitude (EVM), bit error rate (BER), transmit spectrum mask (TSM)). In modern modulation schemes reduction of PAPR is important requirement for distortion free and energy-efficient operation of power amplifiers (PA). In this paper novel implementation of Peak Windowing method for PAPR reduction in Software Defined Radio (SDR) Base Stations (BS) is presented. The measurement results in terms of EVM and ACPR are given for 5 MHz, 10 MHz, 15 MHz, 20 MHz Long-Term Evolution (LTE) and Wideband Code Division Multiple Access (WCDMA) modulations. In case of 10MHz LTE signal, we achieved PAPR = 8 dB, EVM = 2.0%, ACPR -52dBc at modulated PA output, antenna point.

AIR-COOLED 350 W X-BAND SOLID-STATE POWER AMPLIFIER

In this paper we present the results of the design and production of an air-cooled X-band solid-state power amplifier based on AlGaN/GaN/SiC Schottky FET. The power amplifier includes: preliminary power amplifier, output power amplifiers, set of secondary power supplies, digital control unit, monitoring system for the power amplifier performance, set of microwave power waveguide combiners.

Performance analysis of CE-OFDM-CPM Modulation using MIMO system over wireless channels

Orthogonal Frequency-Division Multiplexing (OFDM) is a multicarrier modulation that has expanded attractiveness and is used for wireless communication system. However one key weakness of OFDM signal is the high Peak-to-Average Power Ratio (PAPR). The high PAPR of OFDM signal cause nonlinear distortions by the power amplifier, which in turn affects negatively the OFDM transmission signal. These nonlinearities in amplifiers cause both Inter-Symbol Interference (ISI) and inter-carrier interference (ICI) in the system. A “power back-off” is required to prevent spectral broadening and performance degradation from inter-modulation distortion. To overcome this problem we propose Constant Envelope OFDM (CE-OFDM) which provides a good solution to the high PAPR issue in OFDM. OFDM signal is transformed, by way of Phase Modulation (PM), to a constant envelope signal, thereby alleviating the need for a power back-off and allowing for the most efficient power amplifier operation possible. In this paper the implementation of Maximum-Likelihood Sequence Estimation (MLSE) channel equalization in CE-OFDM-PM is proposed, a performance gain comparison and evaluation over fast fading channels well be presented and discussed. At the same time, Multiple-Input Multiple-Output (MIMO) system is found to provide better performance over wireless channels by providing communication links with substantial diversity and capacity. Likewise for MIMO system, simulation results are given in terms of BER (Bit Error Rate) to show the performance gain of the Alamouti code and of the proposed receiver. The simulation results show that the Minimum Mean Square Error (MMSE) is the best one to avoid ISI.

Performance Evaluation of Digital Pre-Distortion Technique using Low-Complexity and Low-Precision ADC

This paper analyzes the Digital Pre-Distortion linearization technique using a low-precision Analog-to-Digital Converter (ADC). The output of a power amplifier exhibits various spurious emissions, spectral regrowth and intermodulation distortion (IMD) products due to its non-linear behavior. So, to preserve the performance of power amplifier, linearization becomes mandatory. Digital Pre-Distortion does the training on the output of the power amplifier (distorted signal) and generates exactly the inverse characteristics to that of power amplifier. Their cascading results into a linear response. In practical systems, the output of power amplifier has to go through an analog-to-digital converter for digital processing and a low-resolution ADC results in the degradation of the signal and affects the DPD performance. But a low-resolution ADC not only reduces the computational complexity in the digital processing but it also provides lower power consumption and costs less because less hardware would be required. In this work, the aim is to find the precision up to which ADC resolution can be reduced without affecting the DPD performance in a significant manner. This paper evaluates the performance of two DPD systems - Full-band DPD and Sub-band DPD and from simulations, it is observed that for a full-band DPD, 1-bit ADC can be reliably used and for a sub-band DPD, single bit to 4-bits ADC can be used.