Performance Of Tunnel Field-effect Transistor Research Articles

Design and application of germanium based complementary TFET devices with step tunneling paths

Expanding tunneling has consistently been one of the approaches to enhance the on-state current (Ion) and performance of Tunnel Field-Effect Transistor (TFET). This paper proposes a novel structure for TFET called Step Tunneling Path TFET (STP TFET). The stepped tunneling path is achieved by preparing majority carrier channel and introducing pocket doping layers and lightly doped channel extension regions in the channel. Taking Germanium TFET as an example, the complementary structures, electrical parameters, DC and analog characteristics of STP TFET are investigated. Simulation results demonstrate that, compared to normal TFET, STP TFET exhibits significant improvements in Ion (n-TFET∼18/p-TFET∼45 times), cut-off frequency (n-TFET∼6/p-TFET∼16 times), Gain Bandwidth Product enhancement (n-TFET∼22/p-TFET∼16 times), and Transconductance Frequency Product enhancement (n-TFET∼3/p-TFET∼15 times). Furthermore, in the C-TFET inverter, the transient rise and fall times have decreased by 149 and 199 ns, respectively, while the voltage gain has increased by 6.7 times. The proposed device shows promising potential for applications in high-speed and low-power circuit designs.

Tunneling towards efficiency: A survey of design and optimization strategies for tunnel FETs in ultra-low power applications

The tunnel field-effect transistor (TFET) is a promising technology for low-power applications due to its high performance at reduced voltages through quantum tunneling. This article overviews TFETs and their potential to reduce power consumption in digital circuits, analog circuits, and energy harvesting applications. It highlights the challenges faced in TFET design, including gate electrostatics, source doping, and off-state limitations. The importance of design considerations and material selections is discussed, emphasizing their impact on TFET performance. Various fabrication techniques for TFETs are explored, highlighting their significance in achieving efficient and effective devices. The review concludes by stressing the need for further research and development to address existing challenges and unlock the full potential of TFETs in low-power electronic systems.

Room-Temperature Negative Differential Resistance and High Tunneling Current Density in GeSn Esaki Diodes.

Tunnel field-effect transistors (TFETs) are a promising candidate for low-power applications owing to their steep subthreshold swing of sub-60 mV per decade. For silicon- or germanium-based TFETs, the drive current is low due to the indirect band-to-band tunneling (BTBT) process. Direct-bandgap germanium-tin (GeSn) can boost the TFET performance since phonon participation is not required during the tunneling process. Esaki diodes with negative differential resistance (NDR) are used to characterize the BTBT properties and calibrate the tunneling rates for TFET applications. This work demonstrates high-performance GeSn Esaki diodes with clear NDR at room temperature with very high peak-to-valley current ratios of 15-53 from 300 K to 4 K. A record-high peak current density of 545 kA cm-2 at 4 K is also reported for the tensile-strained Ge0.925 Sn0.075 device (strain ≈0.6 %). By applying tensile stresses to n-GeSn epitaxial films, the direct BTBT process dominates, leading to high tunneling rates. Hall measurements further confirm that more electrons populate in the direct Γ valley in the tensile-strained n-GeSn epitaxialfilms.

Modelling and Simulation of Ge Absorber-based Tunnel Field-Effect Phototransistor at 1550 nm

In this article, a semi-analytical model for germanium absorber-based SOI-tunnel field-effect phototransistor at 1550 nm has been proposed. The model works efficiently for a wide range of intensities i.e. 10−2 to 102 µW/µm2 under the application of a very low gate voltage of 0.54 V. Exhaustive simulations using numerical ATLAS 2D device simulation tool with LUMNINOUS optical module have been carried out to propose the merit of tunnel field-effect transistors (TFETs) over metal oxide semiconductor field effect transistors (MOSFETs) for optical applications. The proposed TFET design provides a way to assist the ultrasensitive optical interconnects at a very low gate bias of 0.54 V with a maximum sensitivity of 1.5 × 107, responsivity of 270 mA/W, and detectivity of 3.5 × 1012 Jones at low power density of 0.01 µW/µm2. The TFET performance has further been improved by introducing a heavily doped pocket in between source and channel, which serves as a potential alternative for photodetector applications. The proposed pocket-doped TFET design offers significant improvements in device optical response with optimized sensitivity of 4.1 × 107, a responsivity of 772 mA/W, and a detectivity of 9.9 × 1012 Jones at an optical intensity of 0.01 µW/µm2, gate bias of 0.45 V, and drain voltage of 0.6 V. Transient analysis has been carried out to optimize the response time of the phototransistor for both Ge-gated conventional TFET and pocket-doped architecture and the fall time of ∼0.22 ms has been achieved.

Improving performance of monolayer arsenene tunnel field-effect transistors by defects.

We systematically investigate the transport properties of monolayer arsenene tunneling field-effect transistors (TFETs) along the armchair and zigzag directions using first-principles calculations based on density functional theory (DFT) combined with the non-equilibrium Green's function (NEGF) approach. We introduce five types of defects at the source-channel interface and study their influences on the device performance. The pristine arsenene TFETs along the armchair direction have large ON-state currents due to the small effective masses, but still cannot meet the International Technology Roadmaps of Semiconductor 2022 (ITRS 2022) requirements for high performance (HP) devices. The adsorption of one and two H atoms can significantly enhance the ON-state currents to above 1412 μA μm−1 and reduce subthreshold swing (SS) to below 60 mV decade−1 for both n- and p-type devices, satisfying the ITRS 2022 requirements for HP devices. Besides, the p-type As and the n-type Li adatoms can improve the performance of p-type and n-type devices, respectively. The pristine arsenene TFETs along the zigzag direction with low ON-state currents already meet the ITRS 2022 requirements for low-power (LP) devices. The performance of the p-type TFETs as LP devices can be improved by p-type SV and the As adatom by increasing the ON-state currents and/or reducing the SS. On the other hand, the adsorption of one H adatom can remarkably increase the ON-state current of the p-type TFET to 1563 μA μm−1 and reduce SS to 34 mV decade−1, allowing the device to work as an HP device. We further confirm that the enhancement of the ON-state currents is due to the shortening of the band-to-band tunneling path through the defect induced gap states. Our calculations provide a theoretical guide to improve the performance of TFETs based on arsenene or other monolayer materials by suitable defects.

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the gate stacking, we proposed a tri-layer HfO₂/TiO₂/HfO₂ as a high-K dielectric and hafnium zirconium oxide (HZO) as a ferroelectric (FE) layer. The proposed GAA-TFET overcomes the thermionic limitation (60 mV/decade) of conventional MOSFETs&#x2019; subthreshold swing (SS) thanks to its improved electrostatic control and quantum mechanical tunneling. Simultaneously, the NC state of ferroelectric materials improves TFET performance by exploiting differential amplification of the gate voltage under certain conditions. The most surprising discoveries of this device, which outperforms all previous results, are the very high <inline-formula> <tex-math notation="LaTeX">$I_{ON}/I_{OFF}$ </tex-math></inline-formula> ratio on the order of 10¹¹ and the enormous on-state current of 135 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula>. The incorporation of the NC effect with a 9 nm HZO results in the lowest <i>SS</i> of 20.56 mV/dec (52.38&#x0025; lower than baseline TFET) and the highest voltage gain of 6.58. Furthermore, the output characteristics revealed a large transconductance (<inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula>) of 7.87 mS (10³ order higher than the baseline TFET), drain-induced barrier lowering (DIBL) of 9.7 mV, and a threshold voltage of 0.53 V (37.65&#x0025; lower than baseline TFET), all of which are significant. Thus, all of the results indicate that the proposed device structure may lead to a new route for electronic devices, creating higher speed and lower power consumption.

Optimization and Performance Prediction of Tunnel Field‐Effect Transistors Based on Deep Learning

AbstractThe tunnel field‐effect transistor (TFET) is considered to be a suitable substitute for metal oxide semiconductor‐field effect transistors in the post‐“Moore's Law” era owing to its low power consumption. However, Si‐TFETs face the drawbacks of low on‐state currents and significant ambipolar leakage. This study proposes a GeSi/Si heterojunction double‐gate TFET with a T‐channel hetero‐gate dielectric (HJ‐HGD‐DGTFET) structure to overcome these problems. It also presents a novel method of predicting and optimizing the performance of the existing TFETs which use deep learning to accelerate the device design. Furthermore, this study proposes a neural network based on different requirements to perform two functions: prediction of the device performance using the forward design, and the forecast of the device structure using the inverse design. It can thus be used to determine whether the output of the network meets the design objectives and if it is necessary to change the output by adjusting the input, and lastly achieve the TFET performance prediction and device optimization. The proposed method can be used to design TFETs accurately and efficiently even without professional knowledge. This study provides guidance for the design and optimization of TFETs along with other microelectronic devices.

TCAD analysis of tunnel field effect transistor using Ge material for low power application

Low power is important parameter for any semiconductor devices. In transistors the current flow between source to drain through channel region is dependent upon the materials of source, drain and channel. This paper presents a detailed study of the role of Technology Computer-Aided Design (TCAD) simulations of tunnel-field-effect-transistor (TFET) for low power applications with Germanium (Ge) material. Ge has band gap 0.66 V and the most suitable candidate to improve TFET performance. The need and importance of TCAD tool in semiconductor technology development is explained in details in this manuscript. It also elaborates the TCAD techniques for designing a device, parameter extraction and different models that are used to design different TFET structure. TCAD based digital logic design, design for manufacturing, memory designing and reliability study have been also discussed in this paper.

Impact of gate-on-source misalignment on the analog and digital performance of tunnel FET

Impact of gate-on-source misalignment on the analog and digital performance of tunnel FET

Impact of source doping profile on the performance of CNT TFETs and MOSFETs: design aspects for fabrication tolerance

In this work, the effect of the source doping profile due to possible fabrication aspects has been investigated and discussed for both carbon nanotube tunneling field effect transistors (TFETs) and metal oxide semiconductor field effect transistors (MOSFETs). A quantum 2D simulator, which is based on self-consistent solution of non-equilibrium Green’s function and Poisson’s equation, is utilized. It has been found that the source doping gradient remarkably affects the drain current, especially in the case of TFET. This raises the need for fabrication precautions and design to retain higher ON-state current. Besides, the high frequency behavior of TFET and MOSFET structures is inspected in terms of cut-off frequency f T. It is found that the source doping profile has a more significant impact on TFETs than on MOSFETs. For better performance, source doping needs to be abrupt. However, with a small source-gate underlapping, degradations due to gradual doping can be reduced. It is also found that a TFET with source/drain low-k oxide spacer can achieve more immunity to these degradations than the single oxide structure.

A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

Tunnel Field Effect Transistors (TFETs) have emerged as serious contenders for the replacement of traditional MOSFET technology for the future ultra low power Analog/Digital circuit applications because of their unique properties such as Sub-60 mV/decade subthreshold swing (SS), negligible short channel effects (SCEs) and very low off current (IOFF). This review article intensively studies the RF/Analog and DC performance of III-V materials based TFETs. This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance of III-V TFETs. This paper also point outs the impact of temperature, strain, gate metal work function, source-gate overlap and underlap, doping concentration and supply voltage scaling on the DC, RF/Analog characteristics of III-V TFETs.

Linearity performance and intermodulation distortion analysis of D-MOS vertical TFET

Recent trend researches provide potential results of tunnel field effect transistors (TFETs) for being used in many electronic circuit applications. This work studies the comparative analyses of n+ pocket vertical TFET and dual MOSCAP (D-MOS) vertical TFET to determine their compatibility in RF applications. Synopsys TCAD simulation result shows a better ION/IOFF ratio (8.43 × 108), steeper sub-threshold swing (18.67 mV/dec) and an enhanced ambipolarity behavior of the proposed D-MOS VTFET. A comprehensive investigation of both the devices under consideration is performed and comparison has been made on their linearity and intermodulation distortion performances. Certain figure of merits of RF performance such as their higher order transconductance characteristics, second- and third-order voltage intercept points (VIP2 and VIP3), third-order input intercept point (IIP3), third-order intermodulation distortion (IMD3), 1 dB compression point and total harmonic distortions have been explored in this work. From the analyses performed, the proposed dual MOSCAP VTFET is found to be comparatively linear where minimum intermodulation distortions and lesser higher order harmonics are guaranteed. Finally, the status of the proposed TFET is highlighted as an efficient device for RF circuit applications.

Doping-less tunnel field-effect transistors by compact Si drain frame/Si0.6Ge0.4-channel/Ge source

Tunnel field-effect transistors (TFETs) have attracted immense interest as a promising alternative to complementary metal–oxide semiconductors for low-power-consumption applications. However, conventional TFETs introduce both random dopant fluctuations and ambipolar current issues at negative gate voltages for sub-6-nm technology nodes. In this study, we address the performance of charge plasma-driven doping-less TFETs, including sub-3-nm thick compact drain (CD) geometry/SiGe-channel/Ge source layers for suitable bandgap engineering. An ultrathin CD frame and heteromaterials are adopted for use as channels/sources to improve the ambipolarity and ON-state features, respectively. Simulation demonstrates a clear reduction in the ambipolar current from 3.3 × 10−14 to 3.0 × 10−17 A at gate (VG)/drain (VD) voltages of −1.5/1.0 V and an enhancement in the ON-current from 2.0 × 10−5 to 8.6 × 10−5 A at VG = 1.5 and VD = 1.0 V, compared with conventional TFETs. In addition, diverse fabrication-friendly metals applicable to industry fieldwork sites are tested to determine how the metal work functions influence the outputs. The use of Ti/W/Ni as the drain/channel/source materials, respectively, yields an enhanced ambipolar current of 1.2 × 10−20 A and an ON-current of 3.9 × 10−5 A.

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction.

It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

Performance Improvement of Double-Gate TFET Using Metal Strip Technique

In order to overcome the limitations of a tunnel field-effect transistor (TFET) and to enhance its performance, the use of a low work function live strip (LWLS) in a conventional double-gate TFET (DG-TFET) is proposed in this paper. In this novel DG-TFET architecture, named as LWLS-DG-TFET, a metal strip has been implanted in the oxide layer near the source-channel interface. This technique increases the tunneling rate and thus improves the on-current conduction. In this work, a conventional DG-TFET structure in the presence of a metal live strip is studied and analyzed in detail. Moreover, the position of LWLS has been fixed to optimize the TFET performance. The TCAD simulation results show the DC and analog/RF performance improvement of the proposed LWLS-DG-TFET compared to the conventional DG-TFET.

Impact of uniaxial strain on the electronic and transport properties of monolayer α-GeTe

Density functional theory calculations are performed to explore the electronic and transport properties of monolayer α-GeTe under uniaxial strain. It is found that monolayer α-GeTe has an indirect band gap of 1.75 eV and exhibits worthwhile anisotropy along with high electron mobility. The electron mobilities reach 1974 cm2 · V−1 · s−1 and 1442 cm2 · V−1 · s−1 along the zigzag and armchair directions, respectively. When uniaxial strain is applied, our results show an appreciable strain sensitivity of electron mobility. The electron mobility dramatically increases by an order of magnitude around a special strain due to the shifts of conduction band minimum. In addition, we also construct a double gate tunneling field effect transistor (TFET) with a channel of monolayer α-GeTe. The steeper sub-threshold swing and higher ON/OFF ratio are observed by applying tensile strain to the channel. As a result, it indicates that the appropriate strain can significantly improve the performance of α-GeTe TFETs.

Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET

We have investigated the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET). Extensive simulations show that using a hetero-dielectric gate architecture in the lateral direction (non-ferroelectric/ferroelectric/non-ferroelectric) results in more desirable analog/RF characteristics. The proposed structure is compared with conventional tunnel field effect transistors (TFETs) and ferroelectric TFET (FeTFET). Simulation results manifest that HD-FeTFET is superior to other compared structures, and benefits from both ferroelectric and hetero-dielectric structure. Negative capacitance effect in ferroelectric causes a step-up voltage transformer, as a result the subthreshold swing decreases. Owing to two different dielectric constants in the hetero-dielectric structure, the electric field enhances; thereby, the on-state current increases. In this paper, important analog/RF figures of merit, such as cut-off frequency (fT), maximum oscillation frequency (fmax), transconductance frequency product, and intrinsic time delay (τ), are investigated. Also, linearity parameters including VIP2, VIP3, IIP3, and the 1-dB compression point are considered. We achieve average sub-threshold swing of 14 mV for 5 decades for HD-FeTFET, and is improved by ∼ 48% and ∼ 30% for TFET and FeTFET, respectively. Moreover, the ION/IOFF ratio and the on-state current for the proposed structure are 1011 and 5.3 × 10−7 (A/μm), respectively.

Requirements of epitaxially grown InGaAs channel layers for tunnel field-effect transistors

The requirements of the epitaxially grown InGaAs channel layers for tunnel field-effect transistors (TFETs) have been studied by a comparison between the experimental results and technology computer-aided design (TCAD) simulations. It is observed that the threshold voltage (Vth) of InGaAs TFETs with high In contents is shifted more toward the negative bias direction and the off-characteristics are degraded more than that expected in simulation results. These results are attributable to the increase in n-type effective carrier concentration (Nch) in the InGaAs and InAs channels, which can be caused by lattice relaxation because of the large lattice mismatch between the epitaxial layer and the substrate. The use of a thin channel layer with high In content InGaAs and/or InAs can be a solution for achieving high on-current and low off-current simultaneously. It is found that p-type doping in the InGaAs and InAs channels can mitigate the degradation of the cut-off properties. Moreover, it is observed that increased Nch by unintentional Si impurity atoms at the epitaxial layer and the substrate interface can affect the performance of TFETs with thin InGaAs channels, which can be suppressed by introducing an insertional undoped buffer layer. The impact of Nch is also studied for the short channel devices by TCAD simulations. The p-type doping in InGaAs channels can also mitigate short channel effects in comparison to the n-type doping. The carefully controlled epitaxial growth of InGaAs and InAs channel layers with Nch &amp;lt;1 × 1017 cm−3 is required to realize superior performance InGaAs TFETs.

Monolayer MoSe₂-Based Tunneling Field Effect Transistor for Ultrasensitive Strain Sensing

This article presents a detailed investigation of the impact of mechanical strain on transition metal dichalcogenide (TMD) material-based tunneling field-effect transistor (TFET). First, the impact of mechanical strain on material parameters of MoSe2 is calculated using the first principle of density functional theory (DFT) under meta-generalized gradient approximation (MGGA). The device performance of the TMD TFET has been studied by solving the self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. The results demonstrate that both ${I}_{\scriptscriptstyle {\rm {ON}}}$ and ${I}_{\scriptscriptstyle {\rm {OFF}}}$ increase with uniaxial tensile strain, however the change in ${I}_{\scriptscriptstyle {\rm {ON}}}/{I}_{\scriptscriptstyle {\rm {OFF}}}$ ratio remains small. This strain-dependent performance change in TMD TFET has been utilized to design an ultrasensitive strain sensor. The device shows a sensitivity ( $\Delta {I}_{\text {DS}}/{I}_{\text {DS}}$ ) of 3.61 for a strain of 2%. Due to the high sensitivity to the strain, these results show the potential of using MoSe2 TFET as a flexible strain sensor. Furthermore, the strained TFET is analyzed for backend circuit performance. It is observed that the speed and energy efficiency of ten-stage inverter chain based on controlled strain improve substantially in comparison to unstrained TFETs.

Vertical P-TFET With a P-Type SiGe Pocket

Among all material systems currently being exploited for tunnel field-effect transistor (TFET) applications, silicon germanium (SiGe) is most likely to be adopted for the future low power very-large-scale integration (VLSI) technologies due to its VLSI-compatibility, mature synthesis techniques, and tunable bandgap. This article demonstrates experimentally the enhancement of the drive current ( ${I}_{ \mathrm{ON}}$ ) and the reduction in the subthreshold swing (SS) of vertical Si p-TFET by inserting a thin layer of boron-doped Si0.8Ge0.2 ( ${E}_{\text {G}}\sim {1}$ eV) between the source and the channel. Owing to the reduction in the tunneling barrier height and the increased lateral electric field, carrier transport across the tunneling junction is significantly enhanced. By improving the material quality, further enhancement in the device performance is observed. Simulation suggests that the proposed structure serves as an effective method to boost the device performance of TFETs.