Pentacene Transistors Research Articles

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate, bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.

Metal evaporation dependent charge injection in organic transistors

To illuminate a long-term remaining issue on how contact metallization (metal and speed) affects charge injection, we investigated top-contact pentacene transistors using two categories of metals deposited at various rates. Differing from previous studies such as those devoted to morphological influences by microscopy, in this work we concentrated on their electrical characteristics in particular combining the low-frequency noise which provided a direct quantity of trap density and its evolution with respect to contact metal and deposition rate. It turns out that the transistors with noble metal (Au) suffer from metal-diffusion related charge trapping in the pentacene bulk close to the Au/pentacene interface, and this diffusion-limited injection is greatly tuned from bulk to interface by speeding Au deposition which leads to a Schottky-like injection due to the severe thermal damage to the upper pentacene layer. Applying a conventional contacting metal (Cu), however, Ohmic contacts with much fewer traps are always observed regardless of metallization speed. This is attributed to an ultra-thin interlayer of CuxO that guarantees stable Ohmic injection by introducing gap states and protecting the pentacene film so that those transistors appear to be free from Cu metallization. Our results quantitatively show the limiting factors of charge injection for different metals and at various evaporation rates.

Improved charge injection of pentacene transistors by immobilizing DNA on gold source-drain electrodes

We successfully optimized the charge injection of pentacene-based organic thin-film transistors with bottom contact by immobilizing deoxyribonucleic acid (DNA) on gold electrodes. The single-stranded DNA having mercapto group (-SH) was used as the modified layer by molecular self-assembly onto the surface of gold electrodes. The threshold voltage is −10 V, and the field-effect mobility reaches 0.34 cm2/V s, which is comparable with that of typical top-contact devices. Mechanism of performance improvement is due to the high carrier density in contact region attracted by the phosphate group on the DNA backbone increasing the tunneling probability for improved charge injection. Furthermore, the introduction of modified layer significantly enhanced the grain size of pentacene that is beneficial for charge transport, which also is responsible for the improved device performances.

Enhancement of ultraviolet light responsivity of a pentacene phototransistor by introducing photoactive molecules into a gate dielectric

We demonstrated a new approach to fabricate an ultraviolet (UV) photodetector with a pentacene transistor structure where photoactive molecules of 6-[4′-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) were introduced into a poly(methyl methacrylate) (PMMA) gate dielectric. DPA-CM molecules strongly absorb UV light and form stable charge-separation states. When a negative gate voltage was scanned to a gate electrode of the transistor, the charge-separation states of DPA-CM molecules were converted into free electrons and holes. The free electrons traversed and subsequently reached an interface of the PMMA:DPA-CM layer and a polystyrene buffer layer, inducing accumulation of additional holes in a pentacene channel. Therefore, under 2.54 mW/cm2 of 365 nm UV irradiation, a marked increase in drain current by 6.1 × 102 times were obtained from the transistor. Moreover, the phototransistor exhibited a high light responsivity of 0.12 A/W which is about one order of magnitude larger than that of a conventional pentacene phototransistor [Lucas et al., Thin Solid Films 517, 280 (2009)]. This result will be useful for manufacturing of a high-performance UV photodetector.

Understanding Thickness-Dependent Charge Transport in Pentacene Transistors by Low-Frequency Noise

Close correlation between low-frequency noise and charge transport in pentacene transistors is observed. The trap density evolving with pentacene deposition reveals transformation of growth phase and different transport mechanisms. It explains the greatly altered mobility and contact resistance in which the upper surface's trapping plays an important role. Inspecting contact noise shows high density of traps at contacts that result possibly from pyramid like growth of pentacene or contact damage or both.

Controlling of photoresponse properties of pentacene thin film phototransistors by dielectric layer thickness and channel widths

Organic thin film transistors have recently attracted increasing attention due to some features such as their low production cost, flexibility and possibility of large area. In present review, we report the photoresponse performance of the pentacene thin film transistors including electrodes and dielectric layer thickness. The pentacene transistors having various gate thickness and the various channel widths were fabricated and their electrical characteristics were investigated under dark and white light illuminations. The thickness of gate dielectric layer of the pentacene transistors plays role on the photoresponse of the pentacene transistors. Modification of production parameters of the pentacene organic thin film transistors can be exploited in photosensors based upon organic transistors. It is evaluated that these transistors can be used in two-terminal photodetector applications.

The effect of carbon nanotube/organic semiconductor interfacial area on the performance of organic transistors

We show that the performance of pentacene transistors can be significantly improved by maximizing the interfacial area at single walled carbon nanotube (SWCNT)/pentacene. The interfacial areas are varied by anchoring short SWCNTs of different densities (0–30/μm) to the Pd electrodes. The average mobility is increased three, six, and nine times for low, medium, and high SWCNT densities, respectively, compared to the devices with zero SWCNT. The current on-off ratio and on-current are increased up to 40 times and 20 times with increasing the SWCNT density. We explain the improved device performance using reduced barrier height of SWCNT/pentacene interface.

On‐Demand Patterning of Nanostructured Pentacene Transistors by Scanning Thermal Lithography

Thermal scanning lithography is used to pattern semiconducting nanoribbon-like pentacene structures with ultrahigh spatial resolution onto arbitrary substrates in air. The method allows control of the pentacene crystal growth direction and domain-size distribution. By combining these quasi-one-dimensional nanoribbon-like structures with conductive electrodes and a suitable gate dielectric, functional p-channel transistors are demonstrated.

Stability of pentacene transistors under concomitant influence of water vapor and bias stress

Operational stability of bottom gate pentacene based organic field effect transistors (OFETs) under concomitant influence of water vapor and gate bias stress was examined. Two different gate dielectric materials, namely SiO2 and poly-methylmetacrylate (PMMA), were compared. When a positive gate bias stress was applied while the device was maintained under controlled relative humidity (RH), electrical characteristics were drastically affected, especially hysteresis direction and magnitude of ID–VG transfer characteristics. Characteristics evolution was specific to combined influence of bias stress and RH and were at variance to what observed when only RH or bias stress was applied to the sample. Devices with SiO2 and PMMA gate dielectric exhibited radically opposite behaviors indicating of a strong influence of the pentacene/gate dielectric interface on traps formation.

Following Chemical Charge Trapping in Pentacene Thin Films by Selective Impurity Doping and Wavelength‐Resolved Electric Force Microscopy

AbstractCharge trapping is one of several factors that limit the performance of organic electronic materials, yet even in pentacene, a prototypical small‐molecule semiconductor, the precise chemical nature of charge trapping remains poorly understood. Here the effects of three chemical trap‐precursor candidates are examined by layering thin‐film pentacene transistors with different pentacene defect species. The resulting charge trapping is studied in each device via scanning‐probe electric force microscopy coupled with variable‐wavelength sample illumination. Firstly, it is found that layering with pentacen‐6(13H)‐one (PHO) readily produces uniform charge trapping everywhere in the transistor channel, as expected for an active blanket‐deposited trap‐precursor. However, layering with 6,13‐dihydropentacene (DHP) produces fewer, more‐isolated traps, closely resembling the surface potential distribution in pristine pentacene thin films. Secondly, the rates of trap‐clearing versus illuminating wavelength (trap‐clearing spectra) are measured, revealing enhanced trap‐clearing rates at wavelengths assigned to the absorption of either pentacene or the charged trap species. The trap‐clearing spectrum for the PHO‐layered sample closely resembles the spectrum obtained from pentacene aged in a working transistor, while the trap‐clearing spectrum for the DHP‐layered sample resembles the spectrum observed in pristine pentacene. We conclude that PHO competently creates traps in pentacene that match the expected trap‐clearing spectrum for degraded pentacene, while DHP does not, and that the chemical trap species in aged pentacene is very likely PHO+.

Modeling of organic thin film field-effect transistors based on pentacene in saturation regime: Effect of light illumination

Thin film transistor based on pentacene was fabricated on a SiO2/Si substrate by thermal evaporation method at room temperature. Electrical characteristics of the pentacene transistor subjected to a UV light excitation at a wavelength of 365nm were analyzed. Using the variable range hopping model transport (VRH) we have reproduced the mobility of charge carriers under dark and under light illumination in saturation regime. We have presented a method (differential method) that we can extract electrical parameters of this transistor based on pentacene under dark and under light illumination from the first and the second numerical derivative of electrical measurement ID(VG). Finally, we have extracted the electrical parameters, conductance gch and the total resistance RT, of organic TFTs from output characteristics ID(VD) using numerical fit under dark.

Extracting parameters from current–voltage characteristics of pentacene field-effect transistor in saturation region

The pentacene thin film transistor was fabricated on a SiO2 layer by thermal evaporation method. Using the variable range hopping model (VRH), we have calculated the mobility of carrier charges in saturation region. The electrical parameters, conductance gch and the total resistance RT, of the pentacene transistor were extracted using a differential method based on first and second numerical derivatives of electrical measurement. The obtained results are in good agreement with the experimental results.

Low power flexible organic thin film transistors with amorphous Ba0.7Sr0.3TiO3 gate dielectric grown by pulsed laser deposition at low temperature

We deposited amorphous Ba0.7Sr0.3TiO3 (BST) on silicon and plastic substrate under 110°C by pulsed laser deposition (PLD) and use it as the dielectric of the organic transistor. Depends on the thickness of BST layer, the highest mobility of the devices can achieve 1.24cm2V−1s−1 and 1.01cm2V−1s−1 on the silicon and polyethylene naphthalate (PEN) substrate, respectively. We also studied the upward and downward bending tests on the transistors and the dielectric thin films. We found that the BST dielectric pentacene transistor can maintain the mobility at 0.5cm2V−1s−1 or higher while the bending radius is around 3mm in both upward and downward bending. Our finding demonstrates the potential application of PLD growth high-k dielectric in the large area organic electronics devices.

Polypyrrole top-contact electrodes patterned by inkjet printing assisted vapor deposition polymerization in flexible organic thin-film transistors

Highly conductive polymer, polypyrrole (PPy) was successfully patterned as source and drain (S/D) electrodes for flexible pentacene thin film transistors in top-contact structure by combining inkjet printing and vapor deposition polymerization. Facile inkjet printing of initiator and subsequent exposure of pyrrole monomers resulted in selective absorption and polymerization of pyrrole monomers on the patterned initiator region. Pentacene transistors based on printed PPy electrodes exhibited higher electrical characteristics than that of the devices with thermally evaporated Au electrodes. Improved performance of the devices based on PPy electrodes could be attributed to the reduction of contact resistance at the interface between polymer and organic semiconductor. For the replacement of metal electrodes, vapor deposition polymerization assisted inkjet printing technique can provide a versatile method to utilize highly conductive polymer as a functional electrode of flexible organic electronic devices.

Low-cost lithographically patterned source/drain bottom contacts for high mobility p-type organic thin film transistors

ABSTRACTShort channel organic thin film transistors in bottom-gate, bottom contact configuration use typically gold metallization for the source and drain contacts because this metal can easily be cleaned from photoresist residuals by oxygen plasma or ultraviolet-ozone and allows also surface modification by self-assembled monolayers (e.g. thiols). Alternative low-cost bottom contact metallization for high performance short-channel organic thin film transistors are scarce because of the incompatibility of the bottom contact material with the cleaning step. In this work a new process flow, involving a temporary thin aluminum protection layer, is presented. Short channel (3.4 μm) pentacene transistors with lithographical defined and thiol modified silver source/drain bottom contacts (25 nm thick, on a 2 nm titanium adhesion layer) prepared according to this process achieved a saturation mobility of 0.316 cm2/(V.s), and this at a metal cost below 1% of the standard 30 nm thick gold metallization.

Controlled performance of an organic transistor memory device with an ultrathin LiF blocking layer

In this paper, the controlled performance of a novel organic pentacene transistor memory device with an ultrathin LiF blocking layer was investigated. Our results demonstrate the introduction of an ultrathin LiF layer has a significant influence on the transistor memory performance. As the LiF thickness increased from 0 to 3 nm, the charge carrier mobility showed a three-fold increase from 0.15 to 0.43 cm2 V−1 s−1 due to hole injection enhancement. Moreover, the on/off current ratio increased from 5 to 50 at long measurement times. This significant enhancement of charge retention behavior (∼10 times improvement) was ascribed to the LiF blocking effect when the trapped charge was released from silver nanoparticle induced trap centers. However, the memory window showed a slight decrease from 60 to 37 V, which is due to the decreased penetration depth of silver nanoparticles into the pentacene layer. The physical origin of the memory effect with the LiF ultrathin layer was also discussed. Our introduction of an ultrathin LiF layer offers a simple and feasible way to control the different memory performances of this novel transistor memory device.

The effects of the surface morphology of poly(3,4-ethylenedioxythiophene) electrodes on the growth of pentacene, and the electrical performance of the bottom contact pentacene transistor

An investigation is presented of the effect of the surface roughness of poly(3,4-ethylenedioxythiophene) (PEDOT) electrodes on the growth of pentacene and the electrical performance of PEDOT electrode bottom contact pentacene transistor. Smooth PEDOT films contained well-oriented and small sized pentacene islands whilst rough PEDOT films exhibited randomly oriented islands with non-uniformly sized islands. In addition, PEDOT electrodes provided morphological continuity at the electrode–channel interface, making the accumulation channel of the pentacene formed on the electrodes a main contributor to the contact resistance. Accordingly, the smooth PEDOT surface yielded the low contact resistance (5.7 kΩ cm), approximately half of that obtained with the rough surface.

The immobilization and electrical response of single-stranded DNA molecules on pentacene transistors

The immobilization and electrical response of single-stranded deoxyribonucleic acid (ssDNA) on pentacene-based transistors have been studied. The result displays that ssDNA molecules may be well immobilized onto pentacene film surface observed by atomic force microscopy. The device parameters of transistors including drain-source current and threshold voltage exhibit an obvious change by comparing with pristine transistors that can be attributed to the additional positive charges induced by immobilized ssDNA molecules. Furthermore, the dependence of electrical response on the ssDNA solution concentration was disclosed.

P‐109: Sol‐Gel Alumina Dielectric for Low‐Voltage Operating Pentacene Transistor

AbstractWe present a sol‐gel based aluminum oxide dielectric for organic transistors. The pentacene transistor fabricated with the dielectric permits low voltage operation, exhibits no hysteresis, and is stable when subjected to bias stress. The off‐state current is stable and it is not sensitive to the off‐state voltage.