Peak-to-valley Current Ratio Research Articles

NDR Behavior of a Phosphorous-Doped Double-Gate MoS2 Armchair Nanoribbon Field Effect Transistor

This paper presents the negative differential resistance (NDR) behavior of an MoS2 armchair nanoribbon double-gate field effect transistor. The large peak-to-valley current ratio (PVCR) of 2.58 × 102 with a peak current value of − 0.8 μA is achieved with the presented device configuration. A 5-nm channel length device was considered for the study and an extended Huckel model with nonequilibrium Green’s function method is used for the simulation. A phosphorus atom is used as a substitutional dopant at the sulfur site of the MoS2 field effect transistor near the source and drain regions. The PVCR of the device can be controlled by applying a gate voltage. The achieved subthreshold slope of the device is 88 mV/decade with Ion/Ioff value of 1011 at 300 K. The other parameters such as peak current and NDR voltage window are analyzed. The proposed device configuration shows the potentiality of MoS2 armchair nanoribbon material for future small length scale electronic device applications.

Nitrogen-doped NDR behavior of double gate graphene field effect transistor

Abstract This paper presents the negative differential resistance (NDR) behavior of double gate graphene field effect transistor. The channel length of the device is considered as 4 nm and source/drain regions are doped with nitrogen atoms. The carrier transport is assumed to be ballistic for the simulation. The semi-empirical Slater-Koster method is used to model the material and Nonequilibrium Green's Function (NEGF) is used for the electron transport study of the device. The NDR behavior of the device is discussed by using the transmission spectrum and device density of state (DDOS). The peak to valley current ratio (PVCR) of 105 is achieved with the peak current of -0.6 μA at room temperature. The other parameters like the NDR voltage window and the peak value of drain current are also discussed quantitatively. The simulation study shows the importance of graphene for negative differential resistance for future scaled electronic device applications.

Esaki Diode in Undoped Silicon Film

An Esaki diode with a peak-to-valley-current ratio (PVCR) of 3.59 is demonstrated at 77 K in ultrathin undoped fully depleted silicon-on-insulator (FD-SOI) film. For the first time, the high doping required for band-to-band tunneling (BTBT) is replaced with electrostatic doping in a virtual diode configuration. By manipulating the front- and back-gate bias, a virtual P–N junction with adjustable doping can be emulated. The negative differential resistance (NDR) is captured at a low temperature for high concentrations of free electrons and holes. The electrostatic Esaki diode is fully compatible with current FD-SOI CMOS technology and does not require elaborate doping tailoring. The difference between Esaki diodes with virtual or physical doping is outlined. The simulations show that the BTBT is no longer 1D, as it can occur diagonally through the body due to the asymmetric position of front- and back-gates. The impact of gates biasing and the optimization trends are discussed.

P‐Type Doped AlAsSb/GaSb Resonant Tunneling Diode Photodetector for the Mid‐Infrared Spectral Region

AbstractMid‐infrared (MIR) resonant tunneling diode (RTD) photodetectors based on a p‐type doped AlAsSb/GaSb double‐barrier quantum well (DBQW) are proposed and investigated for their optoelectronic transport properties. At room temperature, a distinct resonant tunneling current with a region of negative differential conductance is measured. The peak‐to‐valley current ratio (PVCR) is 1.51. To provide photosensitivity within the MIR spectral region, a lattice‐matched quaternary low‐bandgap GaInAsSb absorption layer with cutoff wavelength of λ = 2.77 μm is integrated near the DBQW. Under illumination with infrared light, photogenerated minority electrons within the absorption layer can drift toward the DBQW, where they accumulate and cause a shift of the current–voltage characteristics toward smaller bias voltages, which can be exploited to measure the incident MIR light power. In a tunable diode laser absorption spectroscopy experiment, the RTD photodetector is used to identify three distinct water absorption lines in the MIR close to λ = 2.61 μm. By adjusting the absorption layer doping concentration, the RTD quantum efficiency can be increased by a factor of 10, resulting in a sensitivity of S = 2.71 A W−1, which corresponds to an estimated multiplication factor of M = 8.6.

Evaluation of Room-Temperature Performance of Ultra-Small Single-Electron Transistor-Based Analog-to-Digital Convertors

In this paper, in order to analyze the performance of single-electron transistor (SET)-based analog-to-digital converter (ADC) circuits at room temperature, first, the quantum Coulomb blockade regime is explained and based on it we calculate and discuss the inherent Coulomb oscillation characteristics of room-temperature-operating SETs (or, in other words, ultra-small SETs). Then, to explain the performance of SET-based ADC structures, we explore the sensitivity of converter section of these structures to the inherent periodic oscillation characteristics. By simulating two different temperatures of 100[Formula: see text]K and 300[Formula: see text]K, we demonstrate that for proper performance of converter section of the SET-based ADCs, SETs must have inherent Coulomb oscillations with the same and high peak-to-valley current ratio (PVCR) and equal Coulomb peak spacing (i.e., equal [Formula: see text]. The Coulomb oscillation characteristics of the room-temperature-operating silicon SET show the Coulomb oscillations with unequal PVCRs and unequal Coulomb peak spacings (i.e., unequal [Formula: see text]. As a result, it can be seen that the room-temperature-operating SET-based ADCs never have a suitable output.

Wigner Transport Simulation of Resonant Tunneling Diodes with Auxiliary Quantum Wells

Resonant-tunneling diodes (RTDs) with auxiliary quantum wells (e.g., emitter prewell, subwell, and collector postwell) are studied using a Wigner transport equation (WTE) discretized by a thirdorder upwind differential scheme. A flat-band potential profile is used for the WTE simulation. Our calculations revealed functions of the auxiliary wells as follows: The prewell increases the current density (J) and the peak voltage (Vp) while decreasing the peak-to-valley current ratio (PVCR), and the postwell decreases J while increasing the PVCR. The subwell affects J and PVCR, but its main effect is to decrease Vp. When multiple auxiliary wells are used, each auxiliary well contributes independently to the transport without producing side effects.

Theoretical investigation into negative differential resistance characteristics of resonant tunneling diodes based on lattice-matched and polarization-matched AlInN/GaN heterostructures

In this work, we report an investigation of resonant tunneling diodes (RTDs) with lattice-matched and polarization-matched AlInN/GaN heterostructures using the numerical simulation. Compared with the lattice-matched AlInN/GaN RTDs, the RTDs based on polarization-matched AlInN/GaN hetero-structures exhibit symmetrical conduction band profiles due to eliminating the polarization charge discontinuity, which achieve the equivalence of double barrier transmission coefficients, thereby the relatively high driving current, the high symmetry of current density, and the high peak-to-valley current ratio (PVCR) under the condition of the positive and the negative sweeping voltages. Simulations show that the peak current density approaches 1.2 × 107 A/cm2 at the bias voltage of 0.72 V and the PVCR approaches 1.37 at both sweeping voltages. It also shows that under the condition of the same shallow energy level, when the trap density reaches 1 × 1019 cm−3, the polarization-matched RTDs still have acceptable negative differential resistance (NDR) characteristics, while the NDR characteristics of lattice-matched RTDs become irregular. After introducing the deeper energy level of 1 eV into the polarization-matched and lattice-matched RTDs, 60 scans are performed under the same trap density. Simulation results show that the degradation of the polarization-matched RTDs is 22%, while lattice-matched RTDs have a degradation of 55%. It can be found that the polarization-matched RTDs have a greater defect tolerance than the lattice-matched RTDs, which is beneficial to the available manufacture of actual terahertz RTD devices.

Tunable Negative Differential Resistance in MISIM Tunnel Diodes Structure With Concentric Circular Electrodes Controlled by Designed Substrate Bias

The tunable negative differential resistance (NDR) characteristics of metal–insulator–semiconductor–insulator–metal (MISIM) tunnel diodes (TDs) structure with thin oxide were observed by biasing the substrate simultaneously with one of the TDs under designed voltage drops ( $\Delta \text{V}$ ). An inner circular electrode TD surrounded by a ring-shape electrode TD gate pattern was adopted. The NDR region can be adjusted by varying the $\Delta \text{V}$ between the inner TD and the body. Not only the peak-to-valley current ratio (PVCR) but also the voltage range where NDR occurs can be controlled. It is supposed that the injected electrons and the inversion charges increase and decrease with negative bias, respectively, for the MIS(p) TD and play an important role in this observation. Meanwhile, the asymmetry of inner gate and ring gate enhances the coupling efficiency at reverse bias region. In this paper, the PVCR can be tuned to more than two orders and the voltage of the NDR region can be shifted to larger than 1 V. The tunable NDR characteristic of MISIM provides a possible application of MIS TD.

GaSb/AlAsSb resonant tunneling diodes with GaAsSb emitter prewells

We investigate the electronic transport properties of GaSb/AlAsSb double barrier resonant tunneling diodes with pseudomorphically grown ternary GaAsxSb1-x emitter prewells over a broad temperature range. At room temperature, resonant tunneling is observed and the peak-to-valley current ratio (PVCR) is enhanced with the increasing As mole fraction from 1.88 (GaAs0.07Sb0.93 prewell), to 2.08 (GaAs0.09Sb0.91 prewell) up to 2.36 (GaAs0.11Sb0.89 prewell). The rise in PVCR is attributed to an enhanced carrier density at the Γ-valley within the emitter prewell. On the contrary at cryogenic temperatures, increasing the As mole fractions reduces the PVCR. At a temperature of T=4.2 K, reference samples without incorporation of an emitter prewell containing As show PVCRs up to 20.4. We attribute the reduced PVCR to a degraded crystal quality of the resonant tunneling structure caused by As incorporation and subsequently an enhanced defect scattering at the interfaces.

Effect of doping on the transport properties of single-walled carbon nanotube two probe systems

This paper reports the doping induced negative differential resistance (NDR) in chromium substituted zig-zag (4, 0) single walled carbon nanotube (SWCNT) devices and the effect of the doping level on this property by using non-equilibrium Green's function theory formalism in combination with semi-empirical extended Huckel theory (EHT) calculations of the Atomistic Tool Kit software in device mode. The results show that the tunneling current, number of NDR peaks and the conductance increases with an increase in the level of doping. The high peak to valley current ratio (PVR) of the three proposed models are presented in the form of tables for comparative studies. The highest peak to valley current ratio of 5.70 is found in the two atom chromium doped SWCNT geometry. It is believed that the explored chromium doped CNT devices in this study will find number of applications in the future, particularly for fast switching and high speed signal processing.

Resonant Tunneling through Monolayer Si Colloidal Quantum Dots and Ge Nanocrystals

Resonant tunneling through a 4 nm nanocrystal Ge (nc‐Ge) layer and a 2.4 nm monolayer of Si colloidal quantum dots (QD) is achieved with 0.7 nm amorphous Al2O3 (a‐Al2O3) barriers. The nc‐Ge resonant tunneling diode (RTD) demonstrates a peak‐to‐valley current ratio (PVCR) of 8 and a full width at half maximum (FWHM) of 30 mV at 300 K, the best performance among RTDs based on annealed nanocrystals. The Si QD RTD is first achieved with PVCRs up to 47 and FWHMs as small as 10 mV at room temperature, confirming theoretically expected excellences of 3D carrier confinements. The high performances are partially due to the smooth profile of nc‐Ge layer and the uniform distribution of Si QDs, which reduce the adverse influences of many‐body effects. More importantly, carrier decoherence is avoided in the 0.7 nm a‐Al2O3 barriers thinner than the phase coherence length (≈1.5 nm). Ultrathin a‐Al2O3 also passivates well materials and suppresses leakage currents. Additionally, the interfacial bandgap of ultrathin a‐Al2O3 is found to be similar to the bulk, forming deep potential wells to sharpen transmission curves. This work can be easily extended to other materials, which may enable resonant tunneling in various nanosystems for diverse purposes.

Humidity sensing and resonant tunneling properties of indium nitride p-n device

Indium nitride (InN) and indium nitride compound doped oxygen element (InN:O) compounds are grown for application in sensing devices along with the function of microwave properties. The peak-to-valley current ratio (PVCR) of InN/InNO/In/SiO2/Si (III-S) p-n sensing device reached 2.6. The peak current density and peak voltage of the III-S device were as high as 3.67kA/cm2 and 2.2V, respectively. The sensing periods were 580s and 600s for the adsorption and desorption processes, respectively. The sensing sensitivities at a low RH% from 40% to 70% and at a high RH% from 70% to 90% were 8.3mΩ/RH% and 7.5mΩ/RH%, respectively. The resistive cutoff frequency of an III-S device reached 28GHz at an RH of 40%. The sensitivity of frequency measurement for an III-S device for relative humidity was 1.7kHz/RH%.

Memory and negative-resistance effects in a strained metal-gate high-k n-type field-effect-transistor from 375 K down to 77 K

We introduce an experimental alternative way of looking into the charging and discharging mechanism inside a high-k stacked oxide of a metal-gate strained n-type Field-Effect-Transistor (nFET). This alternative way reproduces a memory and negative resistance effect by biasing the nFET device in a non-conventional way. This is achieved by forward-biasing the drain-bulk junction and by setting the gate electrode in a high-impedance mode. The produced negative resistance effect (NRE) has a controllable peak-to-valley current ratio (PVCR) that goes from about 3.0 up to a value of 5.5 at room temperature. The PVCR increases up to 8.35 at T = 225 K and reduces to 2.84 at T = 375 K in a linear trend. The memory effect is observed when the drain-bulk junction voltage is swept from low to high values and back from high to low values. From low to high forward drain-bulk bias the NRE shows up and vanishes when coming back from high to low forward drain-bulk bias. The NRE and memory effects are attributed to a coupled-gate oxide charging/discharging mechanism with an induced bipolar transistor action in the channel of the FET.

Tunnel Dielectric Field-Effect Transistors with High Peak-to-Valley Current Ratio

We present silicon-compatible tunnel dielectric field-effect transistors with strong negative differential resistance. On-state tunneling currents have been improved and fully suppressed ambipolarity with lowest subthreshold slope (SS) 10 mV/dec. In addition to the TFET mode, our device works as the negative transconductance characteristic that produces a high current peak-to-valley current ratio (PVR) (up to 107). Numerical simulations demonstrate the impact of tunnel dielectric layer thickness, gate oxide thickness and temperature on the PVR. With the significant improvement in SS, on-state current and high PVR, this tunnel dielectric transistor provides an effective technique for enhancing the drive current, and realizes its applications in logic and memory circuits.

Performance analysis of single‐electron transistor at room‐temperature for periodic symmetric functions operation

For the first time, the authors have investigated the analysis of the room-temperature operation of single-electron transistor (SET) for periodic symmetric functions (PSFs). They demonstrate that in SETs due to the Pauli exclusion principle the distance between current peaks against bias voltage in coulomb oscillations will be asymmetric. Also, because the separated energy levels have unequal tunnel-barrier resistance, different tunnelling current rates are obtained for each level. So, the unequal peak-to-valley current ratio (PVCR) will be observed in the coulomb oscillations, and therefore the operation of room-temperature of silicon SET-based PSFs is impossible.

Negative differential resistance in BN co-doped coaxial carbon nanotube field effect transistor

The CNTFETs are the most promising advanced alternatives to the conventional FETs due to their outstanding structure and electrical properties. In this paper, we report the I-V characteristics of zig-zag (4, 0) semiconducting coaxial carbon nanotube field effect transistor (CNTFET) using the non-equilibrium Green's function formalism. The CNTFET is co-doped with two, four and six boron-nitrogen (BN) atoms separately near the electrodes using the substitutional doping method and the I-V characteristics were calculated for each model using Atomistic Tool Kit software (version 13.8.1) and its virtual interface. The results reveal that all models show negative differential resistance (NDR) behavior with the maximum peak to valley current ratio (PVCR) of 3.2 at 300 K for the four atom doped model. The NDR behavior is due to the band to band tunneling (BTBT) in semiconducting CNTFET and decreases as the doping in the channel increases. The results are beneficial for next generation designing of nano devices and their potential applications in electronic industry.

Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode

The transfer characteristics of a metal-insulator-semiconductor (MIS) tunnel diode (TD) controlled by a separated MIS TD as gate were investigated. Negative transconductance (NT) exists around the flat-band region in the transfer curve even though the separation between the gate and the MIS TD is large (up to several tens of micrometers). We called it remote gate-controlled NT (RG-NT). With the aid of the Technology Computer Aided Design simulation, the turn around behaviors of the lateral electric field and electron concentration around the flat-band region explain well the RG-NT phenomenon. The peak-to-valley current ratio (PVCR) of the RG-NT increases with the tunnel oxide thickness. The maximum PVCR obtained in this work is $1.3 \times 10^{6}$ while the oxide thickness is 3.3 nm.

Multiple Negative Differential Resistance Device by Using the Ambipolar Behavior of Tunneling Field Effect Transistor with Fast Switching Characteristics.

We propose a novel double-peak negative differential resistance (NDR) characteristic at the conventional single-peak MOS-NDR circuit by employing ambipolar behavior of TFET. The fluctuated voltage transfer curve (VTC) from ambipolar inverter is analyzed with simple model and successfully demonstrated with TFET, as a practical example, on the device simulation. We also verified that the fluctuated VTC generates additional peak and valleys on NDR characteristics by using circuit simulations. Moreover, by adjusting the threshold voltage of conventional MOSFET, ultra-high 1st and 2nd peak-to-valley current ratio (PVCR) over 10(7) is obtained with fully suppressed valley currents. The proposed double-peak NDR circuit expected to apply on faster switching and low power multi-functional applications.

Asymmetric quantum-well structures for AlGaN/GaN/AlGaN resonant tunneling diodes

Asymmetric quantum-well (QW) structures including the asymmetric potential-barrier and the asymmetric potential-well are proposed for AlGaN/GaN/AlGaN resonant tunneling diodes (RTDs). Theoretical investigation gives that an appropriate decrease in Al composition and thickness for emitter barrier as well as an appropriate increase of both for collector barrier can evidently improve the negative-differential-resistance characteristic of RTD. Numerical simulation shows that RTD with a 1.5-nm-thick GaN well sandwiched by a 1.3-nm-thick Al0.15Ga0.85N emitter barrier and a 1.7-nm-thick Al0.25Ga0.75N collector barrier can yield the I-V characteristic having the peak current (Ip) and the peak-to-valley current ratio (PVCR) of 0.39 A and 3.6, respectively, about double that of RTD with a 1.5-nm-thick Al0.2Ga0.8N for both barriers. It is also found that an introduction of InGaN sub-QW into the diode can change the tunneling mode and achieve higher transmission coefficient of electron. The simulation demonstrates that RTD with a 2.8-nm-thick In0.03Ga0.97N sub-well in front of a 2.0-nm-thick GaN main-well can exhibit the I-V characteristic having Ip and PVCR of 0.07 A and 11.6, about 7 times and double the value of RTD without sub-QW, respectively. The purpose of improving the structure of GaN-based QW is to solve apparent contradiction between the device structure and the device manufacturability of new generation RTDs for sub-millimeter and terahertz applications.

Novel five-state latch using double-peak negative differential resistance and standard ternary inverter

We propose complement double-peak negative differential resistance (NDR) devices with ultrahigh peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with conventional CMOS and its compact five-state latch circuit by introducing standard ternary inverter (STI). At the “high”-state of STI, n-type NDR device (tunnel diode with nMOS) has 1st NDR characteristics with 1st peak and valley by band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT), whereas p-type NDR device (tunnel diode with pMOS) has second NDR characteristics from the suppression of diode current by off-state MOSFET. The “intermediate”-state of STI permits double-peak NDR device to operate five-state latch with only four transistors, which has 33% area reduction compared with that of binary inverter and 57% bit-density reduction compared with binary latch.