PCI Express Research Articles

Development of Phased Array Ultrasonic Testing System Using Distributed Architecture

Abstract With more rigorous requirements for reliability and safety of structures and materials, high resolution and fast imaging have been urgent needs of Phased Array Ultrasonic Testing (PAUT). In order to improve the detection resolution and efficiency of complex structures and materials such as ultra-thick carbon steel and honeycomb plate, a PAUT system is proposed in this paper. The system uses a distributed architecture, which not only divides hardware resources, improves system performance, but also is scalable. PA, single- and multi-channel conventional UT, and TOFD (Time Of Flight Diffraction) modalities are combined, and PA modality is carried by the fully parallel non-multiplexed 128 PE (Pulse Echo) electronics with independently adjustable emitting and receiving parameters. In addition, the ultrasound analog front-end circuit is designed using discrete devices, providing more powerful analog performance than integrated chips. GTX (Gigabit Transceiver) and PCIe (Peripheral Component Interconnect Express) are applied to high-speed data transmission, providing raw ultrasound data. Characterization and verification results indicate that the system is ideal for challenging inspections in many industries.

Design and Implementation of Optimized PCI Express Physical Layer for High-Speed and Low-Latency Data Transfer

The PCIe (Peripheral Component Interconnect Express) Protocol is crucial for establishing high-speed data communication between computer peripherals, such as graphics cards and network cards etc. This communication protocol is transmitting data in packet format, with each packet containing both data and destination address and other essential information for accurate data delivery. This paper focused on Physical Layer to achieve High-Speed Data Transmission by reducing delay parameter. To minimize disturbances and enhance reliability, the physical layer uses scrambling technique and an 8b – 10b encoding technique is used for synchronization and error detection. Additionally, SIPO and PISO converts data format to improve efficiency and accuracy. The design is implemented using the Cadence compiler targeting 45nm process technology. This design is delay efficient resulting in path delay of 5.0ns and the operating frequency of 200MHz, power consumption of 1.2mw and an area of 1999µm².

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance.

System for the fast readout and tests of pixel IC operating in single photon counting mode using PCIe-based FPGA

Hybrid Pixel Detectors (HPDs) have become popular in particle and photon detection techniques in recent years. This type of devices consists of two parts: a pixelated sensor (based on Si, Ge, GaAs, CZT, etc.), and a readout Integrated Circuit (IC), which usually contains thousands of pixels and millions of transistors. ICs suffer from the inaccuracies of manufacturing processes, therefore HPDs have to be thoroughly tested before the sensor bump-bonding process. This paper presents a highly efficient system for the automated testing of pixelated HPDs. The presented solution is based on the Intel Arria 10 GX Field Programmable Gate Array (FPGA) development kit and a Linux-powered Personal Computer (PC), connected via Peripheral Component Interconnect Express (PCIe) 8x Gen. 3 interface. The proposed system has been built of well-thought-out modules connected through the set of precisely defined interconnects. This approach enabled the development of an architecture that may be easily implemented in both PCIe-based systems and System-on-Chip devices, such as Intel Agilex SoC. The presented system has been tested with both a manufactured IC and a model implemented in the FPGA.

Scalable Data Concentrator with Baseline Interconnection Network for Triggerless Data Acquisition Systems

Triggerless data acquisition systems (DAQs) require that the data stream is transmitted from multiple links and into the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network’s operation enabled increased scalability compared to the previously published concentrator based on an 8 × 8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were performed for four and five layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware were successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency.

The HSPC — a high speed PCIe readout card for the HFRS-TPC

A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.

A Compact Broadband Common-Mode Suppression Filter That Integrates Series-Mushroom into Defected Corrugated Reference Plane Structures.

This paper proposes a common-mode noise suppression filter scheme for use in the servers and computer systems of high-speed buses such as SATA Express, HDMI 2.0, USB 3.2, and PCI Express 5.0. The filter uses a novel series-mushroom-defected corrugated reference plane (SMDCRP) structure. The measured results are similar to the full-wave simulation results. In the frequency domain, the measured insertion loss of the SMDCRP structure filter in differential mode (DM) can be kept below -4.838 dB from DC to 32 GHz and can maintain signal integrity characteristics. The common-mode (CM) suppression performance can suppress more than -10 dB from 8.81 GHz to 32.65 GHz. Fractional bandwidth can be increased to 115%, and CM noise can be ameliorated by 55.2%. In the time domain, using eye diagram verification, the filter shows complete differential signal transmission capability and supports a transmission rate of 32 Gb/s for high-speed buses. The SMDCRP structure filter reduces the electromagnetic interference (EMI) problem and meets the quality requirements for the controllers and sensors used in the server and computer systems of high-speed buses.

Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.

Readout Electronics for Spatial Distribution Measurement of Neutron Beam Flux in BNCT

Boron neutron capture therapy (BNCT) is a promising cancer treatment that selectively destroys tumor cells using a neutron beam. However, accurately and fast measuring the spatial distribution of neutron flux is critical to ensuring effective treatment. To address this challenge, Micromegas detectors are applied for the first time to measure the spatial distribution of neutron beam flux in BNCT. Due to the high flux, large area, and multiple components of the BNCT beam, the design of readout electronics that can handle high counting rate, large channel numbers, high integration, and discrimination of multiple beam components is challenging. This paper proposes a targeted readout electronics system to overcome this challenge. A modular readout structure based on the PCI Express (PXIe) platform is designed for 384-channel readout. A fully parallel readout structure is developed and fast shaper parameters are optimized to achieve high counting rate for each readout channel. A multi-channel high-speed, large-capacity caching technique is developed to address the high-speed data storage problem. Digital shapers are implemented in field-programmable gate array (FPGA) to achieve high integration. Tests demonstrate that each readout channel can support a counting rate of 800 kHz and achieve an excellent position resolution of 1.4 mm. Furthermore, final tests on the BNCT beam confirm that our system can successfully measure the flux spatial distribution of different neutron components.

A Novel Wideband Common-Mode Noise Suppression Filter That Combines Mushroom and Defected Corrugated Reference Plane Structures

A novel wideband common-mode (CM) suppression filter is proposed for high-speed transmission. The filter is embedded in 3 10 mm × 10 mm layers of a printed circuit board (PCB) that combines a mushroom structure and a defected corrugated reference plane structure (MDCRP). Using the novel MDCRP structure generates more resonance frequencies in the CM current return path. This generates a wider CM noise suppression performance. We used a simulation method to obtain the best geometric parameters for the MDCRP structure. The experimental results proved that the full-wave simulation results were consistent with the actual measurement results. This novel filter shows good signal integrity according to actual measurements, and the insertion loss can be kept to less than −2.306 dB from DC to 21 GHz in differential mode (DM). The CM noise can be suppressed by over −10 dB from 5.09 GHz to 20.62 GHz. The fractional bandwidth is 120.8%, and the CM noise improves by 64.5%. An eye diagram proves that the filter can support a 20 Gb/s transmission rate with complete differential signal transmission capability. The MDCRP structure filter can support HDMI 2.0, PCI Express 4.0, USB 3.2, and SATA Express. Therefore, the filter meets current computer and server system products’ design needs.

Focus on software, data acquisition, and instrumentation

Focus on software, data acquisition, and instrumentation

Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy

Compute Express Link is an open industry standard interconnect offering caching and memory semantics on top of peripheral component interconnect-Express, with resource pooling and fabric capabilities. In addition to providing high-bandwidth and low-latency connectivity between host processor and accelerators, smart network interface cards, and memory expansion devices, it also enables resource pooling across multiple systems for scalable, power-efficient, and cost-effective computing. This article delves into the microarchitectural design to deliver power-efficient performance based on our experience designing a Xeon central processing unit and field-programmable gate array with this technology with demonstrated silicon interoperability.

Wideband common‐mode suppression filter using defected corrugated reference plane structures

AbstractThis article describes a broadband common‐mode filter for suppressing common‐mode (CM) noise in high‐speed differential signals. The filter used a novel defected corrugated reference plane (DCRP) structure. It used structure changes to impact the characteristic impedances in the CM current return path, which caused many approach transmission zeros. The main purpose generated a larger CM noise stopband effect. The experimental results showed that the frequency domain can reduce the CM noise over 9.29 dB from 3.67 to 17.03 GHz. The fractional bandwidth was 129%. The CM noise can be improved by 68.2%. The insertion loss in differential mode (DM) was kept at less than −1.611 dB from DC to 20 GHz with good signal integrity. The eye diagram can support a 16 Gb/s transmission rate in the time domain. The DCRP structure filter supports high‐speed computer buses up to PCI Express 4.0, SATA Express, HDMI 1.4, and USB 3.2, which meet current computer products' needs.

Efficient Crash Consistency for NVMe over PCIe and RDMA

This article presents crash-consistent Non-Volatile Memory Express (ccNVMe), a novel extension of the NVMe that defines how host software communicates with the non-volatile memory (e.g., solid-state drive) across a PCI Express bus and RDMA-capable networks with both crash consistency and performance efficiency. Existing storage systems pay a huge tax on crash consistency, and thus cannot fully exploit the multi-queue parallelism and low latency of the NVMe and RDMA interfaces. ccNVMe alleviates this major bottleneck by coupling the crash consistency to the data dissemination. This new idea allows the storage system to achieve crash consistency by taking the free rides of the data dissemination mechanism of NVMe, using only two lightweight memory-mapped I/Os (MMIOs), unlike traditional systems that use complex update protocol and synchronized block I/Os. ccNVMe introduces a series of techniques including transaction-aware MMIO/doorbell and I/O command coalescing to reduce the PCIe traffic as well as to provide atomicity. We present how to build a high-performance and crash-consistent file system named MQFS atop ccNVMe. We experimentally show that MQFS increases the IOPS of RocksDB by 36% and 28% compared to a state-of-the-art file system and Ext4 without journaling, respectively.

Real-time performance improvement approach based on FPGA in OFDR system

This paper presents a novel approach to accelerate the data processing rate in optical frequency-domain reflectometry (OFDR) system. In conventional solution, data is sampled by data acquisition card and then sent to personal computer (PC) for data processing through high-speed interface such as peripheral component interconnect express (PCIE) and so on. But frequently-used general laptop can’t provide this interface. What’s more, long time is necessary to complete the calculation in PC due to the limitations of serial processing in central processing unit (CPU). To improve the real-time performance of OFDR system, in our work, field-programmable gate array (FPGA) is used as hardware circuit to complete the calculation task and then send the results to PC only to display through universal asynchronous receiver/transmitter (UART) interface in the OFDR system simultaneously. In this way, the refresh rate of output can be accelerated about 50 times, which means the real-time performance of the system is improved a lot.

Improving GPU performance in multimedia applications through FPGA based adaptive DMA controller

Purpose Deep learning techniques are unavoidable in a variety of domains such as health care, computer vision, cyber-security and so on. These algorithms demand high data transfers but require bottlenecks in achieving the high speed and low latency synchronization while being implemented in the real hardware architectures. Though direct memory access controller (DMAC) has gained a brighter light of research for achieving bulk data transfers, existing direct memory access (DMA) systems continue to face the challenges of achieving high-speed communication. The purpose of this study is to develop an adaptive-configured DMA architecture for bulk data transfer with high throughput and less time-delayed computation. Design/methodology/approach The proposed methodology consists of a heterogeneous computing system integrated with specialized hardware and software. For the hardware, the authors propose an field programmable gate array (FPGA)-based DMAC, which transfers the data to the graphics processing unit (GPU) using PCI-Express. The workload characterization technique is designed using Python software and is implementable for the advanced risk machine Cortex architecture with a suitable communication interface. This module offloads the input streams of data to the FPGA and initiates the FPGA for the control flow of data to the GPU that can achieve efficient processing. Findings This paper presents an evaluation of a configurable workload-based DMA controller for collecting the data from the input devices and concurrently applying it to the GPU architecture, bypassing the hardware and software extraneous copies and bottlenecks via PCI Express. It also investigates the usage of adaptive DMA memory buffer allocation and workload characterization techniques. The proposed DMA architecture is compared with the other existing DMA architectures in which the performance of the proposed DMAC outperforms traditional DMA by achieving 96% throughput and 50% less latency synchronization. Originality/value The proposed gated recurrent unit has produced 95.6% accuracy in characterization of the workloads into heavy, medium and normal. The proposed model has outperformed the other algorithms and proves its strength for workload characterization.

Energy-Efficient Encoding for High-Speed Serial Interfaces

Energy consumption has become a bottleneck in modern integrated circuits (ICs) with a significant part of the energy spent on data communication. High-speed, serial interfaces are widely used, offering important advantages over parallel buses. The energy demand of source synchronous, serial buses can be effectively decreased by employing encoding techniques that reduce the bit transitions of the transmitted data stream. However, these techniques are not applicable for asynchronous interfaces, such as Peripheral Component Interconnect Express (PCIe), where frequent bit transitions are required to recover the clock at the receiver to maintain link integrity. Recognizing this fundamental trait, an encoding technique named serial tuned transition encoding (STTE) is proposed that regulates the number of transitions such that the clock can be reliably recovered, while the communication energy is lowered. The proposed scheme provides at least 25% decrease in energy for a short interposer-based interconnect compared to scrambling, which is typically used in serializer/deserializer (SerDes) devices. The link integrity is experimentally evaluated using both an electrical and an optical link that interconnect two field-programmable gate array (FPGA) devices. Results demonstrate that STTE successfully preserves link integrity as no errors are induced during transmission. In addition, STTE adjusts the number of transitions, thus allowing energy reduction and link integrity to be traded off.

13.1: Invited Paper: Learnings from Small Form‐Factor Pluggable PC Design for 8K Display

For large form‐factor displays in IOT applications, pluggable PC modules are a popular choice to integrate a media player within the display panel which allows separation of the display and compute module's upgrade. Industry standard examples include the Intel® Smart Display Module (SDM) [1]. New and emerging requirements such as ITU‐R UHD‐2 (commonly referred to as 8K) and advanced connectivity like 5G and Wi‐Fi 6E present unique signal integrity, connector selection, component and antennas placement challenges which are covered in this paper with key learnings from real world Intel® SDM designs. Key learning one is to leverage investment in industry standards such as PCI Express when implementing a custom interface connector between display panel and compute module for parts availability and cost effectively scaling to new data rates. Second key learning is to ensure the wireless antennas are strategically placed to achieve desired isolation, efficiency, and gain within small form‐factor. A third key learning in enabling 8K to support wide range of display panels by choosing compatible system components and designing correct end to end display signal chain.

An experimental study of group-by and aggregation on CPU-GPU processors

Hash-based group-by and aggregation is a fundamental operator in database systems. Modern discrete GPUs (graphics processing units) have been considered to accelerate the performance. However, the data transfer through the PCIe (peripheral component interconnect express) bus would reduce gains. On recent architectures, the GPU and the CPU (central processing unit) are built into the same chip which removes the data transmission and offers new performance opportunities. Yet there has been no systematic analysis of grouping and aggregation algorithms on such architectures. In this paper, we study the behaviors of various hash-based grouping and aggregation methods on coupled architectures to provide meaningful guidelines. We conduct an extensive experimental study and analysis on the single CPU, the coupled GPU, and both processors. Six dimensions are considered in analyzing the hashing methods carefully: (1) hashing scheme, (2) hash function, (3) data size, (4) group cardinality, (5) load factor, and (6) data distribution. Two additional dimensions are also explored: (7) shared and independent hash tables and (8) running on single processors and co-processing. We hope the results in our study could help database researchers to choose the right direction in terms of algorithm design and system optimization.