Abstract
A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.
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