Abstract
Compute Express Link is an open industry standard interconnect offering caching and memory semantics on top of peripheral component interconnect-Express, with resource pooling and fabric capabilities. In addition to providing high-bandwidth and low-latency connectivity between host processor and accelerators, smart network interface cards, and memory expansion devices, it also enables resource pooling across multiple systems for scalable, power-efficient, and cost-effective computing. This article delves into the microarchitectural design to deliver power-efficient performance based on our experience designing a Xeon central processing unit and field-programmable gate array with this technology with demonstrated silicon interoperability.
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