A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things

Abstract

The Internet of things (IoT) is leading the world into a future of ubiquitous connectivity. The heterogeneity within the IoT domain necessitates a highly flexible, secure, dependable, and energy-efficient IoT processor architecture. In this paper, we propose a novel processor architecture for IoT that renders energy efficiency, high-performance, flexibility, security, and dependability to meet the diverse application requirements. To address the stringent energy efficiency demands of IoT devices, we propose a two-tiered heterogeneous processor architecture that is composed of a high-performance optimized reconfigurable host processor which controls a number of low-power optimized interface processors. The proposed IoT architecture also incorporates reconfigurability in host processors' computing and communication parameters and co-processor extensions to impart flexibility and additional energy savings. The proposed IoT architecture contains various security co-processor extensions to support various security primitives including encryption and decryption, key generation, integrity verification, and device authentication. Finally, the proposed architecture incorporates reliability and dependability through various hardware-and software-based fault tolerance methods. Experimental results present and compare microarchitecture configurations for host and interface processors obtained through an efficient design space exploration methodology. We have implemented selected security and dependability primitives of our proposed IoT architecture on a Xilinx Spartan-6 field-programmable gate array (FPGA). Results reveal that our proposed IoT architecture can attain a speedup of 47.93x while consuming 2.4x lesser energy for furnishing security and dependability primitives as compared to an optimized ARM implementation of similar security and dependability primitives.