Patterned Si Substrates Research Articles

Self-Equilibration of the Diameter of Ga-Catalyzed GaAs Nanowires.

Designing strategies to reach monodispersity in fabrication of semiconductor nanowire ensembles is essential for numerous applications. When Ga-catalyzed GaAs nanowire arrays are grown by molecular beam epitaxy with help of droplet-engineering, we observe a significant narrowing of the diameter distribution of the final nanowire array with respect to the size distribution of the initial Ga droplets. Considering that the droplet serves as a nonequilibrium reservoir of a group III metal, we develop a model that demonstrates a self-equilibration effect on the droplet size in self-catalyzed III-V nanowires. This effect leads to arrays of nanowires with a high degree of uniformity regardless of the initial conditions, while the stationary diameter can be further finely tuned by varying the spacing of the array pitch on patterned Si substrates.

Mediated Electrochemical Deposition of Copper and Silver Thin Films for Improved Resistivity, Grain Size and Intrinsic Stress

INTRODUCTION Copper interconnects are typically grown electrochemically as electrodeposition provides a means of depositing large amounts of material over complex geometries and is easily scalable. However, electrodeposition generally results in film microstructures that adversely affect resistivity and electromigration properties. Electromigration rates increase due to surfaces and grain boundaries, and this problem may worsen as smaller device scales lead to larger surface area to volume ratios. Chemical additives are typically used in electrolytes in order to mitigate these problems. Several additives often must be used to manufacture a high quality film, and the relative concentrations of additives can have significant impact on the microstructure of the film. Unfortunately these additives are poorly understood, and their effects are complex and empirically derived, which slows improvements in electrodeposition processes that rely on these additives. Mediating electrochemical deposition with under potentially deposited (UPD) monolayers of another elemental metal provides a controllable means of affecting the microstructure of the deposited film. The technique requires only one additive to the deposition solution, the mediating metal. This mediator must meet only a few characteristics. The mediating element must be less noble than, exhibit under potential deposition on, and not alloy with the deposited metal. The technique has been previously demonstrated for silver deposition on a single crystal gold substrate. [1,2] In this study, we extend the process to electrodeposition of silver and copper on industrially relevant polycrystalline substrates. RESULTS AND DISCUSSION We investigated UPD mediated electrodeposition of silver and copper films on polycrystalline substrates using lead as the mediating element. We varied the deposition potential to change the coverage of the UPD metal during electrodeposition, and this change in coverage caused a change in the growth mechanism of the depositing film. Silver films were deposited on polycrystalline gold films from 0.1M perchloric acid, 0.01M lead perchlorate and 0.5 mM silver perchlorate solutions. Copper films were deposited on Si substrates with polycrystalline copper seed films from 0.01M lead perchlorate and 0.01M copper perchlorate solutions. The copper films were deposited on silicon substrates as blanket films and patterned lines. We present resistivity data that demonstrate improvement over unmediated growth. In situ stress measurements of the growing films indicate UPD deposition significantly reduces the intrinsic stresses of deposited films. Atomic force microscopy images of the films are presented to show the effects of UPD on growth mechanism, surface roughness and grain sizes. We present Rutherford backscattering data to show the purity of the deposited films. Finally, we report the filling characteristics of UPD mediated deposition of Cu films on patterned Si substrates. Based on experimental results, we discuss how mediated deposition can be applied to improve the quality of electrodeposited copper for interconnect applications to improve electrical resistivity. We also discuss how this deposition technique might be applied to other film/substrate systems to tailor resistivities, intrinsic stresses, and microstructures of electrodeposited films. We also propose that the demonstrated correlation between intrinsic film stress, grain size and resistivities might be used for qualitative characterization of deposited films. The authors gratefully acknowledge materials support from Dr. Qiang Huang of IBM T. J. Watson Research Center. The authors gratefully acknowledge the support of NSF Award Number 1309849. 1. K. Sieradzki, S.R. Brankovic, and N. Dimitrov, Electrochemical Defect-Mediated Thin-Film Growth, Science, Vol. 284, pp. 138-141 (1999). 2. S.R. Brankovic, N. Dimitrov, K. Sieradzki, Surfactant Mediated Electrochemical Deposition of Ag on Au(111), J. Electrochem. Soc., Vol. 2, pp. 443-445 (1999). Figure 1

III–V site-controlled quantum dots on Si patterned by nanoimprint lithography

We have successfully grown regular arrays of InAs/GaAs quantum dots on patterned Si substrates. Thanks to the capability of nanoimprint lithography, we were able to obtain uniform patterns extended over some cm2 areas, with periods of 300nm. Ex-situ and in-situ treatments of the surface allowed us to completely remove any residual oxides prior to growth without the use of hydrogen beams, at temperatures compatible with standard III–V molecular beam epitaxy. The growth protocol was optimized in order to obtain a perfect selectivity of InAs/GaAs nanostructures in the holes, without any deposition on the planar areas.

Growth and characterization of semi-polar (11-22) GaN on patterned (113) Si substrates

Patterned (113) Si substrates have been fabricated for the growth of (11-22) semi-polar GaN, which completely eliminates one of the great issues in the growth of semi-polar GaN on silicon substrates, ‘Ga melting-back’. Furthermore, unlike any other mask patterning approaches which normally lead to parallel grooves along a particular orientation, our approach is to form periodic square window patterns. As a result, crack-free semi-polar (11-22) GaN with a significant improvement in crystal quality has been achieved, in particular, basal stacking faults (BSFs) have been significantly reduced. The mechanism for the defect suppression has been investigated based on detailed transmission electron microscopy measurements. It has been found that the BSFs can be impeded effectively at an early growth stage due to the priority growth along the 〈0001〉 direction. The additional 〈1-100〉 lateral growth above the masks results in a further reduction in dislocation density. The significant reduction in BSFs has been confirmed by low temperature photoluminescence measurements.

Effect of pressure on the semipolar GaN (10-11) growth mode on patterned Si substrates**Project support by the National High Technology Research and Development Program of China (Green Laser).

In this paper, we investigate the effect of pressure on the growth mode of high quality (10-11) GaN using an epitaxial lateral over growth (ELO) technique by metal organic chemical vapor deposition (MOCVD). Two pressure growth conditions, high pressure (HP) 1013 mbar and low pressure growth (LP) 500 mbar, are employed during growth. In the high pressure growth conditions, the crystal quality is improved by decreasing the dislocation and stack fault density in the strip connection locations. The room temperature photoluminescence measurement also shows that the light emission intensity increases three times using the HP growth condition compared with that using the LP growth conditions. In the low temperature (77 K) photoluminescence, the defects-related peaks are very obvious in the low pressure growth samples. This result also indicates that the crystal quality is improved using the high pressure growth conditions.

Periodically structured Si pillars for high-performing heterojunction photodetectors

A periodical array of silicon (Si) micro pillar structures was fabricated on Si substrates using PR etching process. Indium tin oxide (ITO) layer of 80nm thickness was deposited over patterned Si substrates so as to make ITO/n-Si heterojunction devices. The influences of width and period of pillars on the optical and electrical properties of prepared devices were investigated. The surface morphology of the Si substrates revealed the uniform array of pillar structures. The 5/10 (width/period) Si pillar pattern reduced the optical reflectance to 6.5% from 17% which is of 5/7 pillar pattern. The current rectifying ratio was found higher for the device in which the pillars are situated in optimum periods. At both visible (600nm) and near infrared (900nm) range of wavelengths, the 5/7 and 5/10 pillar patterned device exhibited the better photoresponses which are suitable for making advanced photodetectors. This highly transmittance and photoresponsive pillar patterned Si substrates with an ITO layer would be a promising device for various photoelectric applications.

Radial InP/InAsP/InP heterostructure nanowires on patterned Si substrates using self-catalyzed growth for vertical-type optical devices

Radial InP/InAsP/InP heterostructure nanowires (NWs) on SiO2-mask-pattered Si substrates were reported using self-catalyzed InP NWs. Self-catalyzed growth was performed using low growth temperatures and high group-III flow rates, and vertical InP NWs were formed on the mask openings. The diameter and tapering of the self-catalyzed InP NWs were controlled by the introduction of HCl and H2S gases during the NW growth, and InP NWs that have a straight region with decreased diameter were formed. Radial InP/InAsP/InP quantum wells (QWs) were grown on the sidewall of the vertical InP NWs on Si substrates. Room-temperature photoluminescence of single NWs from the QW was clearly observed, which exhibited the potential of building blocks for vertical-type optical devices on Si substrates.

Self-catalyzed InP Nanowires on Patterned Si Substrates

ABSTRACTSelf-catalyzed growth of position-defined InP nanowires (NWs) was investigated on SiO2-mask-pattered Si substrates using metalorganic vapor-phase epitaxy. Using low growth temperatures and high group-III flow rates, pyramidal InP NWs were formed vertically on the mask openings. The diameter and tapering of the InP NWs were successfully controlled by the introduction of HCl and H2S gases during the NW growth. In addition, crystal growth of radial InP/InAsP/InP quantum wells on the sidewall of the InP NWs was performed on Si substrates.

Ordering of low-density Ge quantum dot on patterned Si substrate

We present a study on the growth of a low-density ordered Ge quantum dot (QD) on a nanohole patterned Si (0 0 1) substrate with periods in the order of microns by molecular beam epitaxy. Ordered Ge QDs with different periods were realized, the largest period being 15 µm. From the height-profile evolution of the QD with Ge deposition, it was found that the nanohole filling started at the initial Ge deposition, indicating an immediate nucleation and growth of QDs inside the nanoholes. Such a phenomenon is attributed to a lower surface chemical potential (SCP) inside the nanoholes, which is supported by calculated results on SCP evolution with growth and verified by the observation that the Ge adatoms around the nanoholes exhibited a higher probability of being incorporated into the nanoholes. In this scenario, low density ordered Ge QDs with any large periods could be achieved. The optical properties of the Ge QDs showed a remarkable improvement after a post-growth rapid thermal annealing treatment.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?

This study relates to the heteroepitaxy of InP buffer on patterned Si substrates using the selective area growth in trenches approach. We demonstrated in a first part a high control of the two-step InP buffer growth in STI trench width under 50 nm. In a second part, X-ray diffraction reciprocal space maps, rocking curves and pole figures were used to analyze the crystallinity and defect density of the InP layer.

Transparent conductor-Si pillars heterojunction photodetector

We report a high-performing heterojunction photodetector by enhanced surface effects. Periodically, patterned Si substrates were used to enlarge the photo-reactive regions and yield proportionally improved photo-responses. An optically transparent indium-tin-oxide (ITO) was deposited on a Si substrate and spontaneously formed an ITO/Si heterojunction. Due to an electrical conductive ITO film, ITO/Si heterojunction device can be operated at zero-bias, which effectively suppresses the dark current, resulting in better performances than those by a positive or a negative bias operation. This zero-bias operating heterojunction device exhibits a short response time (∼ 22.5 ms) due to the physical reaction to the incident light. We revealed that the location of the space charge region (SCR) is crucial for a specific photon-wavelength response. The SCR space has the highest collection efficiency of the photo-generated carriers. The photo-response can be maximized when we design the photodetector by superposing the SCR space over a corresponding photon-absorption length. The surface enhanced Si pillar devices significantly improved the photo-responses ratios from that of a planar Si device. According to this design scheme, a high photo-response ratio of 5560% was achieved at a wavelength of 600 nm. This surfaced-enhanced heterojunction design scheme would be a promising approach for various photoelectric applications.

(Invited) Three-Dimensional Epitaxial Si1-XGex, Ge and SiC Crystals on Deeply Patterned Si Substrates

We show that geometric shielding of the reactive flux in chemical vapor deposition by tall neighboring structures obtained by deep substrate patterning, along with short surface diffusion lengths, can provide nearly space filling arrays of high-quality epitaxial crystals despite large mismatches of lattice parameters and thermal expansion coefficients. The density of extended defects is strongly reduced by the method, and wafer bowing and crack formation largely inhibited. The concept is shown to be valid for SiGe/Si heterostructures ranging from pure Si to pure Ge both on Si(001) and Si(111) substrates. Here, dislocations are efficiently eliminated from three-dimensional faceted crystals with high-aspect ratios on top of micron-sized Si pillars. The application to 3C-SiC/Si(001) ridges, characterized by a lattice mismatch of nearly 20%, provides significantly lower stacking fault densities compared with layers grown on planar substrates.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor is a winning combination to further boost the performance of future CMOS devices.Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy.We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach on a common Si platform.

Influence of Trench Width on III-V Nucleation during InP Selective Area Growth on Patterned Si(001) Substrate

The integration of III/V materials onto Si substrates is of significant interests for microelectronic and optoelectronic applications. The utilization of the selective epitaxial growth (SEG) on patterned Si substrates by metalorganic vapor phase epitaxy (MOVPE) is proved as a valuable solution for the heteroepitaxy of III-V semiconductors on Si thanks to the “defect trapping” by sidewalls. The demonstration of successful integration by the SEG in wide trenches (above 100nm) is extensively available in the literatures.[1-6] However, following scaling rules for Logic CMOS devices, new challenges are imposed on the heteroepitaxy inside nano-scaled trenches (i.e. sub-50nm trenches for FinFET devices). Therefore, in this study, the influence of trench width on nucleation behavior based on InP SEG in “V-groove” trenches[7,8] as an example, is discussed and analyzed via the proposal of a nucleation model according to the ex-situ morphology observation in the experiments. The evolution of morphology for the selective growth of InP in submicron “V-groove” trenches on on-axis Si(001) substrates is characterized by SEM and AFM. Due to the high lattice mismatch between InP and Si, the typical evolution of 3D islands growth mode in both wide and narrow trenches is identified. The comparison of nominally 40nm to both 150nm and 500nm wide trenches indicates that there is an evolution lag for islands coalescence in narrower trenches. This is the reason for discontinuous topology and highly defective layers obtained in sub-50nm trenches. We believe that one possible mechanism attributing to this lag is induced by greater inter-island distance in narrower trenches. Therefore, we propose a nucleation model to evaluate the influence of trench width on the inter-island distance, suggesting that the scaling relationship between the critical inter-island distance and trench width is theoretically predicted as L* ~W-1/(2i*+4) if W≤2L*in the surface-diffusion limited regime. This understanding is of critical importance for the uniform growth inside nano-trenches for the heteroepitaxy of mismatched III/V compounds onto Si substrates, where the 3D island growth mode dominates in most cases.ACKNOWLEDGMENTSThis work is supported by IMEC Industrial Affiliation Program. The present authors would like to thank the Logic Program and Management, partners.References 1 W.J. Choi and P. Daniel Dapkus, J. Cryst. Growth 195, 495 (1998). 2 G. Wang, M.R. Leys, N.D. Nguyen, R. Loo, G. Brammertz, O. Richard, H. Bender, J. Dekoster, M. Meuris, M.M. Heyns, and M. Caymax, J. Electrochem. Soc. 157, H1023 (2010). 3J.Z. Li, J. Bai, J.M.Hydrick, J.G. Fiorenza, C.Major, M. Carroll, Z. Shellenbarger and A. Lochtefeld, ECS Trans. (2009), pp. 887–894. 4 C. Merckling, N. Waldron, S. Jiang, W. Guo, O. Richard, B. Douhard, a. Moussa, D. Vanhaeren, H. Bender, N. Collaert, M. Heyns, a. Thean, M. Caymax, and W. Vandervorst, J. Appl. Phys. 114, 033708 (2013). 5 S. F. Cheng, L. Gao, R. L. Woo, a. Pangan, G. Malouf, M.S. Goorsky, K.L. Wang, and R.F. Hicks, J. Cryst. Growth 310, 562 (2008). 6 Y. Dong, Y.L. Okuno, and U.K. Mishra, J. Cryst. Growth 260, 316 (2004). 7M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, and M. Heyns, Cryst. Growth Des.12(10), 4696 (2012). 8 C. Merckling, N. Waldron, S. Jiang, W. Guo, N. Collaert, M. Caymax, E. Vancoille, K. Barla, a. Thean, M. Heyns, and W. Vandervorst, J. Appl. Phys. 115, 023710 (2014).

(Invited) Three-Dimensional Epitaxial Si1-XGex, Ge and SiC Crystals on Deeply Patterned Si Substrates

The heteroepitaxial growth of layers onto substrates differing substantially in lattice parameter and thermal expansion coefficients continues to be a challenge because of the formation of crystal defects, wafer bowing or layer cracking. We have recently demonstrated for the example of Ge/Si(001) that these deficiencies can be avoided by combining deep substrate patterning with appropriately tuned surface diffusion lengths, resulting in dense arrays of highly perfect three-dimensional epitaxial crystals [1]. Here we discuss the extension of the method to layer/substrate combinations with lattice misfits ranging from zero for pure Si/Si(001) up to 20% for 3C-SiC/Si(001).As an example we show in Fig. 1 scanning electron microscopy images obtained on space-filling arrays of Si, Si0.6Ge0.4 and Ge crystals grown to a height of 8 µm onto 2 µm wide pillars separated by 2 µm wide trenches etched to a depth of 8 µm into Si(001). The surface diffusion lengths were kept approximately the same for the three arrays by keeping the deposition rate constant while lowering the substrate temperature from 810° C for Si, to 660° C for the alloy and finally to 485° C for Ge. This is reflected in the remarkably similar crystal morphology for the three cases, characterized by narrow gaps between neighboring crystals and closely similar facet structures. The unusual growth mode of Fig. 1 results mainly from the combination of short surface diffusion lengths below typical facet sizes and reactive flux shielding by neighboring substrate pillars or crystals. While the latter is essentially given by the substrate geometry, tuning of the diffusion lengths by means of substrate temperature may affect the deposition rate. Indeed, the structures of Fig. 1 have been obtained by low-energy plasma-enhanced chemical deposition [2], providing fast, nearly temperature independent deposition rates. The approach is applicable also to off-cut substrates and to other substrate orientations. Figure 2 shows an example of an array of 8 µm tall Ge0.9Si0.1crystals on Si(111) pillars.High-resolution X-ray diffraction with laboratory sources and scanning nano-diffraction by a focused synchrotron X-ray beam proves that the structures of Figs. 1 and 2 are entirely free from misfit and thermal strain [3]. Wafer bowing is virtually eliminated and layer cracks cannot arise.The short surface diffusion lengths required for the growth of 3D crystal arrays can more easily be attained for compound semiconductors. Here the ratio of anion and cation radical fluxes provides an additional control parameter such that molecular beam epitaxy and even chemical vapor deposition (CVD) can be used as deposition tools.We have applied the method outlined above to the growth of 3C-SiC on deeply patterned Si(001) by low pressure CVD. As an example we show in Fig. 3 a cross-section SEM image through 3C-SiC ridges which clearly exhibit the kind of self-limited lateral expansion visible also in Figs. 2 and 3. For high SiC ridges all stacking faults on {111} planes parallel to the ridges escape through the ridge sidewalls.Financial support by the Swiss federal program Nano-Tera through project NEXRAY, by Fondazione Cariplo through the MANDIS project, and by PileGrowth Tech is gratefully acknowledged.[1] C.V. Falub et al., Science 335, 1330 (2012).[2] C. Rosenblad et al., J. Vac. Sci. Technol. A 16, 2785 (1998).[3] C.V. Falub et al., Sci. Rep. 3, 2276 (2013).

Self-catalyzed ternary core-shell GaAsP nanowire arrays grown on patterned Si substrates by molecular beam epitaxy.

The growth of self-catalyzed ternary core-shell GaAsP nanowire (NW) arrays on SiO2 patterned Si(111) substrates has been demonstrated by using solid-source molecular beam epitaxy. A high-temperature deoxidization step up to ∼ 900 °C prior to NW growth was used to remove the native oxide and/or SiO2 residue from the patterned holes. To initiate the growth of GaAsP NW arrays, the Ga predeposition used for assisting the formation of Ga droplets in the patterned holes, was shown to be another essential step. The effects of the patterned-hole size on the NW morphology were also studied and explained using a simple growth model. A lattice-matched radial GaAsP core-shell NW structure has subsequently been developed with room-temperature photoluminescence emission around 740 nm. These results open up new perspectives for integrating position-controlled III-V NW photonic and electronic structures on a Si platform.

Self-organized 2D Ni particles deposited on titanium oxynitride-coated Si sculpted by a low energy ion beam

Self-ordered Ni nanoparticles grown on TiNxOy-coated crystalline silicon previously sculpted by ion beam bombardment are reported. The samples are obtained following a sequential in situ routine deposition procedure. First, crystalline Si is Xe+ bombarded, generating regular patterns. Second, a thin TiNxOy film is grown on the patterned Si substrate. Immediately, nano-sized nickel particles are deposited by ion beam sputtering and temperature-annealed forming a 2D lattice. The self-organized Ni islands are induced by preferential Ni site nucleation on the coated sculpted Si grooves.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor (FinFET) is a winning combination to further boost the performance of future CMOS devices.Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active regions, using nanometer scale trenches with high aspect ratio (>3) in order to eliminate (111)-oriented defects (such as threading dislocations, twins or stacking faults) on the sidewalls. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy (SA-MOVPE). Silicon 300mm wafers substrates patterned with ~300nm deep Shallow Trench Isolation (STI) structures are used with trenches having typical widths ranging from 500 nm down to ~20nm.We report here on the SA-MOVPE growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. The structures are fully characterized by Scanning and Transmission Electron Microscopy, Atomic Force Microscopy, X-Ray Diffraction, Secondary Ion Mass Spectroscopy and Scanning Spreading Resistance Microscopy. We demonstrate the dependence of the material quality and trench filling upon different sets of growth conditions.We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach for advanced III-V based logic devices or III-V based photonic applications on a common Si platform.

Growth of patterned island arrays to identify origins of thin film stress

To understand the origins of stress in thin films, we have used wafer curvature to measure the stress evolution during electrodeposition of Ni on lithographically patterned Si substrates. The stress is measured as the hemispherical islands grow and impinge upon each other, forming interfacial boundaries between them. We relate the results to a model for polycrystalline films in which the stress is attributed to competing processes occurring where the layers in adjacent grains grow into each other and form new segments of grain boundary. This model predicts that the stress in each layer depends on the rate at which the grain boundary is growing when that layer is incorporated into the film. The calculations agree with the measured stress vs thickness using a single set of fitting parameters for five different growth rates.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices

This study relates to the heteroepitaxy of InP buffer and InxGa1-xAs channel layers on patterned Si substrates using the defect trapping technique. We focused on the optimization and control of the InP buffer layer in STI trenches to obtain low defect density and high mobility InxGa1-xAs channel layer. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.