Patterned Si Substrates Research Articles

Ge nanocoatings as anode for three dimensional Si based Li ion microbatteries

Three dimensional (3D) hedgehog-like Ge nanoelectrodes coated on patterned Si substrate are successfully fabricated through the facile chemical vapor deposition (CVD) process. The 3D Si substrate with enlarged surface area and the abundant Ge shell electrode configuration are together favorable to enhance the lithiation/delithiation kinetics during cycling. Impressively, the optimized 3D Si@hedgehog-like Ge (Si@H-Ge) NRs composites anodes embrace high reversible areal capacity and superior rate capability when employed as anode material for 3D Si based lithium ion microbatteries (LIMBs).

Characteristics of Ga-doped ZnO thin-film ultraviolet photodetectors fabricated on patterned Si substrate

Ultraviolet (UV) photodetectors have demonstrated wide applications in both civil and military fields such as pollution monitoring and missile warning. ZnO-based UV photodetectors have attracted tremendous attention due to the advantages of low cost and high chemical and thermal stability. In this work, Ga-doped ZnO (GZO) films were grown with the technique of RF magnetron sputtering and metal–semiconductor–metal (MSM) UV detectors were fabricated with the GZO films as the active detection layers. The as-sputtered films were further treated by the means of thermal annealing such that reduced oxygen vacancy and improved crystallization were achieved for the films. The effect of patterned Si substrates on the GZO UV detectors performance was revealed for the first time. With optimized annealing temperature and delicately designed substrate patterns, the responsibility of GZO MSM photodetectors has been greatly enhanced (e.g. about 2.5-folds higher than ones fabricated on non-patterned Si substrate). Our work on the GZO material and the structural design may pave a new way towards developing low-cost but high-performance UV detectors.

GaAs epilayers grown on patterned (001) silicon substrates via suspended Ge layers

We demonstrate the growth of low density anti-phase boundaries, crack-free GaAs epilayers, by Molecular Beam Epitaxy on silicon (001) substrates. The method relies on the deposition of thick GaAs on a suspended Ge buffer realized on top of deeply patterned Si substrates by means of a three-temperature procedure for the growth. This approach allows to suppress, at the same time, both threading dislocations and thermal strain in the epilayer and to remove anti-phase boundaries even in absence of substrate tilt. Photoluminescence measurements show the good uniformity and the high optical quality of AlGaAs/GaAs quantum well structures realized on top of such GaAs layer.

Semi‐Polar InGaN‐Based Green Light‐Emitting Diodes Grown on Silicon

High‐quality semi‐polar (11‐22) GaN is obtained by means of growth on patterned (113) silicon substrates featured with stripy grooves and extra periodic gaps which are perpendicular to the grooves. Ga melting‐back during the GaN growth at a high temperature is eliminated as a result of special patterning design. On‐axis X‐ray rocking curve measurements show that the linewidth is significantly reduced down to 339 arcsec. Photoluminescence (PL) measurements at 10 K show strong GaN band‐edge emission only, meaning that any basal stacking fault‐related emission is not observed. Furthermore, green InGaN/GaN light‐emitting diodes (LEDs) with an emission wavelength of around 530 nm are achieved on the semi‐polar GaN grown on the patterned Si substrates. Excitation power‐dependent PL measurements do not show a shift in wavelength, meaning a significant reduction in polarization‐induced piezoelectric fields. Electroluminescence (EL) measurements exhibit that the output power of the semi‐polar LED increases linearly with increasing injection current. It is worth highlighting that the overgrowth technology on designed patterned (113) silicon is a potential approach to manufacturing high‐performance semi‐polar GaN emitters on Si substrates in a long wavelength region.

Kinetic mechanism of conformal magnesium silicide (Mg2Si) film formation via reaction of Si single crystals with Mg vapor

Patterned Mg2Si structures can be attractive for use in optoelectronic, thermoelectric, and other devices. Such structures can be fabricated as conformal Mg2Si films on patterned Si substrates via direct reaction of these substrates with Mg vapor at modest temperatures and ambient pressure. Here, we report the kinetic mechanism (rate-limiting step and associated rate law) that controls such vapor/solid reactive formation of conformal Mg2Si films. To avoid oxidation during silicide formation, experiments were conducted within metal ampoules that were sealed in an argon atmosphere. Upon heating each sealed ampoule to 600 °C, Mg vapor (generated from solid Mg sealed within the ampoule) underwent reaction with a Si single-crystal plate (located a fixed distance from the solid Mg within the ampoule). Kinetic data were obtained by evaluating the change in thickness of the product Mg2Si film, and the specimen mass change per area, with reaction time at 600 °C. The changes in mass and in film thickness were both found to follow parabolic kinetics, with the rate constants obtained from both types of measurements in good agreement. Changes in the diffusion distance of the Mg vapor to the reacting Si single-crystal plate, and in the crystal orientation of the plate, were found to have negligible influences on the reaction kinetics. Such data were consistent with solid-state diffusion through the Mg2Si product layer as the rate-limiting step. An inert marker experiment was used to determine the predominant interface at which Mg2Si formed, and to evaluate the rate-limiting species controlling such formation.

Effect of thermal annealing on the interface quality of Ge/Si heterostructures

The performance of X-ray imaging detectors based on epitaxial Ge-crystal arrays grown on patterned Si substrates is severely limited by the presence of misfit and threading dislocations. Here, we study the effect of cyclic thermal annealing on misfit dislocations at the Ge/Si interface. By scanning transmission electron microscopy and energy dispersive X-ray spectroscopy, it is shown that the annealing process promotes the diffusion of Si into the Ge crystal resulting in a corrugated interface and slightly reduces the dislocation density. Finally, our results demonstrate that the thermal process is very effective at eliminating twin boundaries.

Ultra-Energy-Efficient Photoelectrode Using Microstriped GaN on Si

A prototype photoelectrode with a unique design has been fabricated using GaN microstripes grown on a patterned Si substrate. The photoelectrode has demonstrated a record-high photocurrent density of 11 mA/cm2 upon one sun illumination and a H2 generation rate of up to 2.67 mL·cm–2·h–1. This performance with a step-change has been achieved due to the contribution from both the GaN and the silicon substrate, as such a combination covers a wide spectral region (from the ultraviolet region due to the GaN bandgap to the infrared region due to the silicon bandgap). Unlike conventional GaN grown on a silicon substrate, where a thick AlN layer is required to separate GaN from the silicon in order to avoid the well-known Ga melt-back issue, a GaN/silicon heterojunction in our photoelectrode can be formed as a result of a weak Ga melt-back reaction, which is due to the specially designed configuration of our photoelectrode grown using the microstripes. Two reference photoelectrodes have been fabricated for compari...

Cost-effective selective-area growth of GaN-based nanocolumns on silicon substrates by molecular-beam epitaxy

In this paper, the selective-area growth (SAG) of GaN-based nanocolumns (NCs) on silicon (Si) has been investigated experimentally. A low-cost and facile method has been proposed and implemented to fabricate the SAG NCs, which contains the processes of nanosphere lithography (NSL) and plasma-assisted molecular beam epitaxy (MBE). SAG NCs grown by this method indicates a higher ability to modulate the NC distributions than those grown by the conventional patterned method. According to photoluminescence results, InGaN/GaN NCs grown on Si nanopillars produced by NSL and etching show the more uniform indium (In) distribution than those grown on the openings of patterned Si substrate. Furthermore, according to the kinetic processes during MBE growth, it is proposed that the SAG of NCs results from the combination of the shadow effect of Si nano-pillars and the growth suppression of titanium (Ti) film.

In situ dry cleaning of Si wafer using OF2/NH3 remote plasma with low global warming potential

Dry cleaning technology is an essential technique that can be applied to remove native oxide and various contaminants during the semiconductor manufacturing for nanoscale electronic devices. In this study, the in situ dry cleaning of silicon dioxide (SiO2) with low global warming potential (GWP) gas mixtures has been investigated by sequential process steps composed of the reaction of SiO2 surface by oxygen difluoride (OF2) (GWP: <1)/ammonia (NH3) remote plasma and the removal of the reacted compound layer by lamp heating. By using the optimized OF2/NH3 (2:1) mixture for the surface reaction followed by the lamp heating at 200 °C to remove the reacted compound layer, a high-SiO2 cleaning rate and etch selectivity over silicon nitride (>30:1) could be obtained due to the formation of the highest HF concentration on the SiO2 surface at the OF2/NH3 (2:1) gas ratio. The compound layer formed during the reaction was (NH4)2SiF6 observed for a previously investigated NF3 (GWP: 17 200)/NH3 plasma, but the dry SiO2 cleaning rate and the etch selectivity over Si3N4 obtained by the OF2/NH3 plasma were higher than those by the optimized NF3/NH3 plasma. The effects of OF2/NH3 mixture dry cleaning on the electrical characteristics of metal-oxide-semiconductor (MOS) devices fabricated on the nano-scale trench patterned Si substrate with high aspect ratio were studied and compared with conventional wet and NF3/NH3 mixture dry cleaning-based devices. Compared with other cleaning methods, OF2/NH3 dry-cleaning shows the improved and reliable electrical characteristics such as sharper capacitance-voltage behavior, lower hysteresis, less interface trap charge and smaller contact resistivity. Therefore, it is believed that the in situ sequential dry SiO2 cleaning with the OF2/NH3 remote plasma can be applied as an essential cleaning method with extremely low GWP for fabricating next generation nano-scale devices.

Growth temperature dependent strain in relaxed Ge microcrystals

Epitaxial growth of dissimilar materials on patterned substrates is a promising technique for defect-free, monolithic integration of various optoelectronic devices on a single chip. In this work we investigate the structural quality of Ge microcrystal arrays monolithically grown at temperatures ranging from 450 to 575°C on patterned Si substrates. Using high resolution X-ray diffraction with reciprocal space mapping, we obtain the lattice parameters, strain and degree of relaxation. This structural analysis gives us insight in dislocation formation together with quantitative information about thermal relaxation and lattice bending.

Facile morphology control of high aspect ratio patterned Si nanowires by metal-assisted chemical etching

Facile and effective method to fabricate highly ordered silicon nanowires (SiNWs) using metal-assisted chemical etching (MACE) was demonstrated. MACE solutions with various concentrations were studied to understand the etching mechanism for patterned Si substrates with different doping concentrations. MACE rate of Si (100) at different time periods was studied with different doping concentrations (p, p+, n, and n+) at a MACE solution concentration of 5:1:1 for an accurate morphology control and reproducibility of the SiNWs. Based on a four-step model, the SiNW formation mechanism was proposed involving anisotropic etching of SiNWs based on hole transfer between Au/Si interfaces exposed when subjected to MACE solution. Time dependent variation in etch rate of Si to fabricate SiNWs was observed with different doping concentration. The effect of the doping concentration on the etching was revealed based on band diagrams. However, agglomeration of p+-SiNWs was observed, which was attributed to their doping and ability to act against various forces like surface tension during drying. Different aspect ratios of SiNWs were observed for different time periods; n+-SiNWs exhibited the maximum aspect ratio of approximately 81. A visible-light absorbance analysis revealed the potential of the synthesized SiNWs can be good base and host materials for various light harvesting and energy storage devices.

(Invited) Epitaxial Germanium and Germanium Tin Alloys By Thermal Chemical Vapor Deposition

In this work we will discuss the epitaxial growth of both germanium (Ge) and germanium tin (Ge1-xSnx) by thermal chemical vapor deposition. The focus of the discussion is on the challenges we encountered in the development of a low-temperature process to form a Ge layer with a smooth surface and a reasonably low defect level, a Ge1-xSnx layer in a metastable state, or a Ge/Ge1-xSnx stack structure. Examples of surface roughening, relaxation, intermixing, and segregation are given. Device fabrication from individual Ge/Ge1-xSnx layers and stacks will be mentioned. For Ge growth on Si, we further discuss the importance of process conditions both to minimize the in-film defectivity and to enhance the surface smoothness. The growth selectivity to various dielectric materials shows some interesting dependence on in situ doping and other growth parameters. The dependence of film properties, such as crystallinity and resistivity, on substrate type, such as silicon, silicon germanium, and germanium, is studied. Growth on patterned Si substrates will also be discussed. With an optimized low-temperature growth process, Sn can be uniformly distributed in Ge to form a homogeneous phase of Ge1-xSnx. The dependence of growth rate and Sn concentration on the Ge and Sn sources is discussed. Sn concentration up 16% can be achieved with decent film quality on a relaxed Ge layer. Fully strained Ge1-xSnx alloys and Ge/Ge1-xSnx stacks have both been used in the fabrication of electronic and photonic devices. The techniques used in stack formation are discussed together with in situ boron and phosphorus doping of Ge/Ge1-xSnx.

The Growth of GeSn Layer on Patterned Si Substrate by MBE Method

GeSn is an important Si based semiconductor material due to its direct band characteristic. The small amount of Sn into GeSn alloy will induce a high-efficiency optical detection in the full-band communication at low concentration of Sn (approximately 3%). It has attracted lots of attention in recent years. However, due to the low solid solubility of Sn in Ge and large lattice mismatch, the growth of GeSn on Si is still a challenge. High-quality GeSn alloy have been grown by molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), but there is still high the dislocation density. We have reported a new way to grow the defect-free GeSn alloy strips on Si substrates with the assistance of Sn. The lateral growth of GeSn alloy strips were grown on Si(111) by Sn self-catalyzed method. The GeSn materials are grown in a custom-designed MBE system with a base pressure of 5 × 10−8 Pa. The Here the growth of GeSn strips are studied on pattered substrate. We will discuss the growth mechanism and the impact factors on the materials. It is found that Sn has an important impact on morphology of the GeSn materials and different depositions and annealing times of Sn will impact the morphology of the materials. GeSn alloy strips show a good quality by the TEM micrographs and the SAED patterns(Fig.1). No dislocation is found in the grown material. GeSn growth on patterned substrate is also discussed.

The Growth of GeSn Layer on Patterned Si Substrate by MBE Method

A method to grow high quality GeSn alloy strips with assistance of Sn has been developed, and strips grow laterally on Si(111) substrates in molecular beam epitaxy (MBE) chamber. The GeSn heteroepitaxial strip has been proven to be of good crystalline quality without threading dislocations (TDs) by transmission electron microscopy (TEM). In the meantime, introduction of Sn into Ge was investigated by Raman spectra and energy-dispersive X-ray spectroscopy (EDS). In addition, size and density of GeSn strip can be adjusted by changing the growth conditions, and Sn concentration varies approximately linearly against the epitaxial temperature. Moreover, the Hall mobility of GeSn alloy strips at room temperature was 336 cm2·V-1·s-1 and the carrier concentration was 7.9×1012 cm−3 by Hall measurement. Therefore, the proposed method provides an easy technique to grow high quality GeSn materials for Si-based photonics and microelectronics applications

The effect of Ga pre-deposition on Si (111) surface for InAs nanowire selective area hetero-epitaxy

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nucleation. Therefore, gallium incorporation on a Si surface is identified as an important enabler for vertical InAs NW growth. A new method for high yield (&amp;gt;99%) vertical InAs NW SAE on Si using an InGaAs nucleation layer is proposed based on this study.

Strain-Compensated InGaAsP Superlattices for Defect Reduction of InP Grown on Exact-Oriented (001) Patterned Si Substrates by Metal Organic Chemical Vapor Deposition.

We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO2) stripes and oriented along the [110] direction. Undercut at the Si/SiO2 interface was used to reduce the propagation of defects into the III–V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 108/cm2 and 1.2 nm; respectively and 7.8 × 107/cm2 and 10.8 nm for the GaAs-on-Si layer.

Nano crystalline diamond MicroWave Chemical Vapor Deposition growth on three dimension structured silicon substrates at low temperature

Nano crystalline diamond (NCD) films grown at a temperature below 400 °C can open new applications on temperature sensitive substrates such as polymers or low-melting point alloys. One requirement for the applicative use of NCD is the ability of depositing on a structured substrate having high aspect ratio. This work presents a study on the three dimensional (3D) conformity of NCD deposition at low temperature (350 °C) and low pressure (30 Pa). Silicon wafers have been structured using a mask-less photolithography and (hardmask-less) Deep Reactive Ion Etching (DRIE) process and seeded with nano-diamond particles. The NCD films were grown on these 3D patterned Si substrates with various trench geometries to provide means of determining the limiting geometries of this technique. By measuring the step coverage with changing trench width, a threshold for conformal NCD growth can be determined. The NCD films at the bottom of the 100 μm deep trenches were continuous down to an aspect ratio of 1:7.

Crack Statististics and Stress Analysis of Thick GaN on Patterned Silicon Substrate

In this work, crack statistics are developed for MOCVD‐grown 12 μm thick GaN on patterned Si substrate for different sizes, trench widths and trench heights of the mesas. Optical microscope is used to obtain the percentage of cracked mesas in order to develop the crack statistics. The crack statistics show that the size and the trench height of the mesas have large effects on the percentage of cracked mesas but the trench width has no significant effect. The stress on crack‐free thick GaN mesas is investigated by micro‐Raman scattering process at room temperature by varying the size, trench height and trench width of the mesas. Both crack statistics and stress measurement show the similar behavior while varying these features of the mesas. According to Raman analysis, the critical stress for cracking of 12 μm GaN films is about 1.8 GPa.

A-Axis GaN/AlN/AlGaN Core-Shell Heterojunction Microwires as Normally Off High Electron Mobility Transistors.

Micro/nanowire-based devices have been envisioned as a promising new route toward improved electronic and optoelectronic applications, which attracts considerable research interests. However, suffering from applicable strategies to synthesize uniform core-shell structures to meet the requirement for the investigations of electrical transport behaviors along the length direction or high electron mobility transistor (HEMT) devices, heterojunction wire-based electronics have been explored limitedly. In the present work, GaN/AlN/AlGaN core-shell heterojunction microwires on patterned Si substrates were synthesized without any catalyst via metalorganic chemical vapor deposition. The as-synthesized microwires had low dislocation, sharp, and uniform heterojunction interfaces. Electrical transport performances were evaluated by fabricating HEMTs on the heterojunction microwire channels. Results demonstrated that a normally off operation was achieved with a threshold voltage of 1.4 V, a high on/off current ratio of 108, a transconductance of 165 mS/mm, and a low subthreshold swing of 81 mV/dec. The normally off operation may attribute to the weak polarization along semipolar facets of the heterojunction, which leads to weak constrain of 2DEG.

Simulation of Thermoelectric Generator Composed of Nanopatterned Thermoelement

The conversion efficiency of thermoelectric (TE) devices is determined by the dimensionless figure of merit ZT, which is expressed as ZT = S2σT/κ, where S is the Seebeck coefficient, σ is the electrical conductivity, κ is the thermal conductivity, and T is the absolute temperature, respectively. The key strategy to enhance ZT is through decreasing the thermal conductivity of thermoelectric materials. In this study, finite element analysis was used to investigate the effect of stripe-patterned Si substrates on thermal properties of a thermoelectric thermoelement, which consists of PbSe and PbTe thin film layers grown on the periodic patterned Si substrates. The width and depth of the stripe patterns were varied from 10 µm to 0.5 µm to determine their effects on the heat transport in the thermoelement. The calculated results reveal that the depth and width of the stripe patterns play an important role in decreasing the thermal conductivity of the thermoelectric module. The effect of the dimension of the patterns on the effective thermal conductivity of the TE thermoelement was shown in figure 1. The thermal conductivity is lower with respect to the deeper and narrower stripe patterns. The decreased thermal conductivity results from the enhanced phonon-boundary scattering due to the presence of periodic patterns. The phonons can be scattered more extensively when the dimension of the patterns is comparable to the mean free path of TE materials. Therefore, we modeled a thermoelectric generator (TEG) composed of stripe-patterned TE thermoelements taking advantage of its lower thermal conductivity. The dimension of the patterns was optimized selected to generate to achieve a higher power output of TEG. This work demonstrated the feasibility of using nanopatterned thermoelectric (TE) thermoelements to improve TE generator performance. Figure 1