Patterned Ground Shield Research Articles

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor’s Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed.

Determination of the Contribution of the Ground-Shield Losses to the Microwave Performance of On-Chip Coplanar Waveguides

In this article, we characterize and model two parasitic effects that become apparent in the performance of coplanar waveguide interconnects in CMOS. One is the transverse resistance introduced by a patterned ground shield in coplanar waveguide interconnects, which significantly contributes to the shunt losses. The other one is the parasitic coupling between the input and output ports through the ground shield. The latter effect is particularly accentuated in relatively short lines and complicates the determination of the propagation constant using line–line algorithms at several tens of gigahertz. We demonstrate that using the proposed methodology, excellent model–experiment correlation can be achieved in the modeling of these types of interconnects up to at least 60 GHz.

The effect of a metal PGS on the Q ‐factor of spiral inductors for RF and mm‐wave applications in a 28‐nm CMOS technology

In this paper, the effect of a metal patterned ground shield (PGS) on the performance of monolithic inductors is investigated. To this aim, three spiral inductors integrated in a 28-nm fully depleted (FD) silicon-on-insulator (SOI) CMOS technology are analyzed by means of a 3-D FEM-based commercial software. The inductors have been designed at different operating frequencies in the RF and mm-wave ranges to better explore the effect of the PGS. Extensive analysis revealed that the shield is able to improve the quality factor (Q-factor) only of the inductor operated at the lowest frequency (ie, K-band). On the contrary, it has a detrimental effect on the Q-factor of the inductors working at higher frequencies. This is mainly due to induced losses in the PGS itself, which are so high to frustrate the substrate loss reduction. This result gives a different perspective to the adoption of the PGS for CMOS integrated inductors, which is largely recommended to improve inductor performance in the current state of the art.

Patterned Ground Shield for Inductance Fine-tuning

ABSTRACT Post-fabrication inductance variation is a big issue faced by chip designers of sensitive circuits, and on-chip tunable inductors seem to provide the solution to this problem. In addition, tunable inductors also benefit circuits that require the multi-frequency operation. This paper is on the design of a tunable inductor which utilizes the patterned ground shield (PGS) to enable fine-tuning capability. This work is unique as this is the first time that the PGS is used for this purpose, previous researches were more on the Q-factor merit provided by the inductors with PGS. In this work, inductor's and PGS parameters influencing the inductance tuning range and Q-factor performances were first determined. Subsequently, inductors with PGS made from different metals and track spacing were designed, with electronic circuitries implemented to control the grounding of each PGS metal finger. The hypothesis that the floating and grounding of each PGS metal finger can change the magnetic flux of the inductor which contributes to the inductance variation was verified using Sonnet EM. Measured results show that a 5.2% inductance tuning range and Q-factor of 5.9 were achieved at the Bluetooth frequency of 2.5 GHz for an inductor with 2.0 µm track spacing and a polysilicon PGS with finger spacing of 2.0 µm. The tunable inductor was further integrated into a power amplifier (PA) and simulation results show that it enables the PA to achieve the design specification at the frequency range of 3.3–3.8 GHz, dedicated for the sub-6 GHz 5G application.

IMPROVED PERFORMANCE OF LNA USING HIGH QUALITY FACTOR PGS ON-CHIP SPIRAL INDUCTORS

This paper presents a detailed study of on-chip spiral inductors with patterned ground shield (PGS) inserted between the spiral inductorand the silicon substrate. This new design has been implemented in source degeneration cascode lownoise amplifier (LNA) circuit to show how the PGS inductors improve the performance of the circuit. An operation in 1.8V supply voltage, source degeneration cascode LNA structure was studied with both technology and PGS inductors. In this paper, the Agilent ADS (Advanced Design System) simulation software and TSMC 0.18μm CMOS process parameters were adopted to achieve the low-cost characteristics and high integration to fit the performance of 2.4 GHz LNA design under IEEE 802.11a specification.According to the co-simulation results, the forward gain (S21) improved from 13.432 to 21.474 dB, and the (S12)is below the typical value of -15dB. The input impedance (S11) and the output impedance (S22) also represented good performance. In addition, the minimum noise figure was quite good. Thus, the LNA circuit with PGS inductorswas better in the availability and the possibility of 802.11a specification.

A Scalable, Broadband, and Physics-Based Model for On-Chip Rectangular Spiral Inductors

A scalable, broadband, and physics-based compact model for on-chip spiral inductors with rectangular outline shape is demonstrated for the first time in this paper. A simple dc inductance model is developed based on the current sheet approximation. The reduction in inductance due to the flow of eddy current in a back metal plate is considered using the method of images. A three-ladder network is shown to be sufficient to accurately model skin effect caused due to the magnetic field setup at high frequencies. Geometry-dependent expression suitable for rectangular cross-sectional metal strips is presented to predict the proximity effect. Physics-based expression for the substrate capacitance is derived. The proposed model is also shown to have a good correlation in the presence of a patterned ground shield. The proposed model is verified across CMOS process parameters that affect the inductor performance, such as metal thickness, substrate resistivity, and substrate thickness. Furthermore, model accuracy is also validated across design parameters such as spiral width, spacing between turns, number of turns, and diameter. The model is shown to have a good agreement with both EM simulations and measurements.

Electronic controlled CMOS inductor with patterned metal ground shields for fine inductance tuning application

This paper is on an inductance fine tuning technique which benefits from the idea of varying the number of metal plates of an inductor’s pattern ground shield (PGS) shorted to ground to change its magnetic fields. This technique is unique because the geometry and physical shape of the inductor remains untouched from its form in the process design kit (PDK) while the inductance is being tuned. The number of metal shields shorted to ground was controlled by an electronic circuit which consists of analog-to-digital converters and active switches. Both Sonnet EM simulator and Cadence Virtuoso were used for the inductor and circuit simulations. From the simulation, it was found that the inductance increased while the Q-factor decreased as more metal shields were shorted to ground. For instance, at 1.6 GHz, the simulated inductance was 8.8 nH when all metals were floated and 9.4 nH when all metals were shorted to ground. On the other hand, the simulated Q-factor was 10.4 when all metals were floated and 9.8 when all metals were shorted to ground. From both simulation and measured results, both inductance and inductance tuning range increased with frequency. From the measured results too, the inductance observed was 9.4 nH at 1.6 GHz, 10.8 nH at 2 GHz, and 13.5 nH at 2.5 GHz when all the metal shields were shorted to ground. The inductance tuning range was 6.2% at 1.6 GHz, 12.5% at 2 GHz, and 20% at 2.5 GHz. The measured results showed good correlation with the simulated results trend, but with smaller value of inductance, inductance tuning range and Q-factor.

A Novel On-Chip Transformer With Patterned Ground Shield for High Common-Mode Transient Immunity Isolated Signal Transfer

In this letter, a novel on-chip transformer (OCT) with patterned ground shield (PGS) is proposed and demonstrated for high common-mode transient immunity isolated signal transfer. By inserting the PGS between the stacked coils of the OCT, the capacitive coupling between the coils is effectively blocked, whereas the inductive coupling is almost unaffected. Consequently, during common-mode voltage transient, the induced displacement current due to the capacitive coupling is directed to the ground by the PGS instead of going through the secondary coil to affect the output signal. Experimental results show that the proposed OCT with PGS achieved a 27%–92% reduction of the common mode to secondary voltage gain compared to the conventional OCT without sacrificing the inductances, the primary-to-secondary voltage gain, the isolation capability, and the fabrication complexity.

A high‐frequency, low‐coupling 8‐shaped differential inductor with patterned ground shield

AbstractA high‐frequency, low‐coupling 8‐shaped differential inductor with patterned ground shield (PGS) is presented in this paper. The differential structure formed by two single‐inductors in stepping order makes high‐fSR (self‐resonant‐frequency) possible and it also suppresses the far‐field magnetic coupling. A PGS structure not only maximizes the Q‐factor but also improves simulation time and accuracy of EM‐simulation. The test chip is implemented in TSMC 0.18um 1‐poly, 6‐metal CMOS process and the measurement results showed good match with EM‐simulation.

The Performance of an Integrated Transformer in a DC/DC Converter

The separation between the low-voltage part and high-voltage part of the converter is formed by a transformer that transfers power while jamming the DC ring. The resonant mode power oscillator is utilized to allow elevated competence power transfer. The on-chip transformer is probable to have elevated value inductance, elevated quality factors and elevated coupling coefficient to decrease the loss in the oscillation. The performance of a transformer is extremely dependent on the structure, topology and other essential structures that create it compatible with the integrated circuits IC process such as patterned ground shield (PGS). Different types of transformers are modeled and simulated in MATLAB; the performances are compared to select the optimum design. The on-chip transformer model is simulated and the Results of MATLAB simulation are exposed, showing an excellent agreement in radio frequency RF.

Radiofrequency characteristics of ionized sputtered tantalum nitride thin-film resistor in CMOS device

We report the analysis of the radiofrequency (RF) characteristics according to the size, area, and shape of TaN thin-film resistor (TFR) layers. As the TFR size increased, its characteristics were degraded with increasing frequency owing to the increased capacitive parasitic components. As the frequency increased from 1 MHz to 10 GHz, the effective resistance decreased by approximately 12.5%, 16.4%, and 37.8% when the resistor widths and lengths were 0.5 × 20, 1 × 40, and 2 × 80 μm, respectively. To optimize the performance of the high-frequency TFR, ensuring RF isolation via sufficient separation from the silicon substrates was crucial. To realize this RF isolation, methods for minimizing the effect of lossy Si substrates by using TFRs with a smaller area or by forming a patterned ground shield should be introduced.

High performance suspended spiral inductor and band-pass filter by wafer level packaging technology

Suspended inductors and 2.45 GHz BPF with patterned ground shields on the lossy silicon substrate by using Cu/BCB based wafer level packaging and bulk Si etching technologies were fabricated. Thick BCB interlayer is used as the supporting dielectric and the backside cavity is easily removed by using a two-step back-etching process. The fabricated 2.7 nH inductor has a maximum Q factor 49 at 8.2 GHz and high Q factors more than 22 in the broadband frequency range from 1 to 10 GHz. And the realized 2.45 GHz BPF has the insertion loss of 3.0 dB and the return loss of more than 14 dB at the pass band. It is also featured by more than 48 and 25 dB attenuation at 0.9 and 1.8 GHz respectively, with the second harmonic rejection being 33 dB.

Miniaturized low loss 60 GHz CMOS mixed coupled BPF with patterned ground shield

ABSTRACTThis letter presents a miniaturized low loss mixed coupled on‐chip band‐pass filter using overlapped open loop ring resonators and using patterned ground shields. The fabricated prototype shows an insertion loss of 3.7 dB, a return loss > 20 dB, a bandwidth of 13 GHz, and a chip size of 700 μm × 450 μm. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:697–699, 2016

Spiral Inductors With Floating Low-Loss RF Shields for <inline-formula> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> Resonator Applications

A method for designing $LC$ tank circuits to improve energy efficiency and reduce layout area is described. The approach uses a projected shield that is floating, overlaps the trace of the overlying inductor, and adds capacitance to the tank’s inductor. Capacitance is distributed along the spiral traces, and the layout area is thus decreased. In this paper, we investigate the properties of spiral inductors with and without projected shielding, and compare the method with similar circuits including those with floating shields shaped as patterned ground shields. In addition, a measurement methodology for $LC$ tank resonators is developed and presented. Test structures are implemented as microstrip spiral inductors and evaluated as $LC$ tank circuits that resonate between 100 and 500 MHz. The $Q$ values of shielded structures are up to 7% greater than those without shields, and area savings for $LC$ resonators—compared with side-by-side layouts of $L$ and $C$ —are up to 35%.

A 0.07 mm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex></formula> 2.2 mW 10 GHz Current-Reuse Class-B/C Hybrid VCO Achieving 196-dBc/Hz FoM<formula formulatype="inline"><tex Notation="TeX">$_{{\rm A}}$</tex> </formula>

This Letter describes a current-reuse class-B/C hybrid voltage-controlled oscillator (VCO) with robust startup, enhanced phase noise and differential balancing at small area and power. Specifically, an asymmetrical CMOS class-C core is aided by a symmetrical NMOS-only class-B core that effectively shares the bias current for deeper class-C operation of the former; wider margin of startup against PVT variations, and lower amplitude imbalance against oscillation frequencies. Moreover, this topology adds the freedom of adjustable peak dynamic current and boosts the oscillation swing at low power. The spiral inductors with patterned ground shields shrink the die size. Fabricated in 65 nm CMOS, the 0.07 mm $^{2}$ VCO prototype exhibits 10.15-to-11.17 GHz tunability, and ${-}107.73$ -dBc/Hz phase noise at 1 MHz offset, while dissipating merely 2.2 mW at 1.2 V. The achieved area-included figure-of-merit (FoM $_{\rm A} = 196$ dBc/Hz) favorably compares with the state-of-the-art.

A NOVEL WL-INTEGRATED LOW-INSERTION-LOSS FILTER WITH SUSPENDED HIGH-Q SPIRAL INDUCTOR AND PATTERNED GROUND SHIELDS

A novel wafer level integrated low-insertion-loss filter working at 1.8 GHz (DCS LPF) with suspended inductors and patterned ground shields on the lossy silicon substrate is fabricated. Thick BCB interlayer is used as the supporting dielectric, and the backside cavity on Si wafer is formed by using a two-step back-etching process. The influence of patterned ground shields on the Q factor of the suspended inductors and the influence of low-resistivity silicon on the insertion loss of filters are analyzed by EM simulation. The fabricated 2.7 nH inductor has a maximum Q factor of 49 at 8.2 GHz and high Q factors more than 22 in the broadband frequency range from 1 GHz to 10 GHz. And the realized LPF in DCS band has the insertion loss of 0.35 dB and return loss of more than 15.5 dB at the pass band, with the second harmonic rejection being 23 dB and the third harmonic rejection being 38 dB respectively.

A 0.137 mm$^{{2}}$ 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

A compact realization of hybrid class-B/C quadrature voltage-controlled oscillator (QVCO) with output buffering is proposed. It employs a four-phase amplitude detector feedback loop to shift the operation mode from hybrid class-B/class-C to class-C after power up. The power-efficient class-C core allows quadrature-locking via passive capacitive coupling, whereas the auxiliary class-B core ensures a robust startup. For higher output drivability, PMOS-based source followers are stacked atop the QVCO for reusing its bias current and avoiding any AC-coupling networks. The buffered QVCO can directly drive up the 50- Ω port of testers, or to withstand a large capacitive load in on-chip signal distribution. The fabricated 9 GHz QVCO in 65 nm CMOS draws 10.5 mW and exhibits -99.37-dBc/Hz phase noise at 1 MHz offset. The active area is just 0.137 mm 2 by using two compact spiral inductors with patterned ground shields.

Analysis of substrate shielding methods for sub‐THz on‐chip inductors

An analysis of the influence of three substrate shielding methods, unshielded, patterned-ground shield and floating shield, on a sub-terahertz (sub-THz) inductor is presented. In the sub-THz frequency band, the unshielded inductor showed the best quality-factor (Q-factor) and self-resonance frequency (ƒSR) since the inserted substrate shield increases the parasitic capacitance. The simulation results using an electromagnetic simulator showed good agreement with the analysis.

CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

This paper presents CMOS distributed amplifiers (DAs) using the proposed gate-drain transformer feedback technique. The feedback allows reuse of the traveling signal to achieve a high gain-bandwidth product while maintaining low power consumption of DAs. With the folded transmission lines and patterned ground shield, the miniaturized transformer has high quality factors and a well-controlled feedback coupling coefficient. Two DAs are realized using the proposed technique in both 0.18-μm and 90-nm CMOS technologies, respectively. The 0.18-μm CMOS DA achieves a gain of 9.5 dB with a 3-dB bandwidth of 32 GHz, and the noise figure (NF) ranges from 4.1 to 7.6 dB under a power consumption of 71 mW. Under a power consumption of 60 mW, the 90-nm DA demonstrates a gain of 7 dB, a bandwidth of 61.3 GHz, and an NF below 6.2 dB up to 40 GHz. The core areas of the 0.18-μm and 90-nm designs are only 0.58 and 0.41 mm2, respectively.

Micromachined Passive Bandpass Filters Based on GaAs Monolithic-Microwave-Integrated-Circuit Technology

This paper presents micromachined on-chip RF passive bandpass filters at 1-8 GHz based on utilizing a three-pole LC low-pass filter and two dc-blocking capacitors, which is accomplished with a GaAs monolithic-microwave-integrated-circuit process. The microwave design model of the bandpass filters that take into account conductor losses is given and verified. Using this model, the RF bandpass filter with a tunable center frequency and a desirable bandwidth can be realized. Due to only a planar spiral inductor required in the design, the layout size of the filter is less than 700μm × 400μm. Furthermore, in order to minimize the effect of substrate losses caused by the inductor on the bandpass filter, metal shores (MSs) and patterned ground shields (PGSs) are located and inserted between the inductor and the GaAs substrate, respectively, and a cavity on the backside of the inductor substrate is processed by the via-hole etching technique. Measurement results demonstrate that RF bandpass filters without MS and PGS show agreement with the design performance and those with MS and PGS have resulted in the improvement of about 24% insertion loss and a slight effect on the center frequency.