CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

Abstract

This paper presents CMOS distributed amplifiers (DAs) using the proposed gate-drain transformer feedback technique. The feedback allows reuse of the traveling signal to achieve a high gain-bandwidth product while maintaining low power consumption of DAs. With the folded transmission lines and patterned ground shield, the miniaturized transformer has high quality factors and a well-controlled feedback coupling coefficient. Two DAs are realized using the proposed technique in both 0.18-μm and 90-nm CMOS technologies, respectively. The 0.18-μm CMOS DA achieves a gain of 9.5 dB with a 3-dB bandwidth of 32 GHz, and the noise figure (NF) ranges from 4.1 to 7.6 dB under a power consumption of 71 mW. Under a power consumption of 60 mW, the 90-nm DA demonstrates a gain of 7 dB, a bandwidth of 61.3 GHz, and an NF below 6.2 dB up to 40 GHz. The core areas of the 0.18-μm and 90-nm designs are only 0.58 and 0.41 mm2, respectively.