Patterned Ground Shield Research Articles

Micromachined GaAs MMIC-Based Spiral Inductors With Metal Shores and Patterned Ground Shields

This paper presents micromachined GaAs monolithic microwave integrated circuits (MMIC)-based radio frequency (RF) planar spiral inductors with metal shores (MS) and patterned ground shields (PGS). The inductors are fabricated using a GaAs MMIC process without any additional step. MS and PGS are located and inserted between the planar spiral inductors and the GaAs substrate respectively for depressing substrate losses. To further improve its performance, the backside substrate of each inductor is processed to form the membrane structure by the via-hole etching technology. Based on the parameter extraction about a single-ended method, the characteristics of two-type RF spiral inductors (3.5- and 4.5-turn) are investigated. The measured quality factor (Q) of 4 nH on-chip spiral MMIC inductors (4.5-turn) with MS and PGS are 13 at 5.8 GHz and 14.2 at 6.6 GHz, respectively. Measurement results demonstrate that the effects of MS and PGS on the Q of MMIC inductors have resulted in the improvement of about 6% and 15%, respectively, and on the inductance and the metal losses are almost constant in interested frequencies. These improved inductors applied to GaAs MMIC-based passive lowpass filters reduce insertion losses of the filters.

Substrate shielding of transformers in millimeter-wave integrated circuits

Shielding structures intended to improve the performance of millimeter-wave transformers are presented. The loss mechanisms of the components are discussed and the losses related to the silicon substrate are shown to be the most relevant. A patterned ground shield and a floating shield are detailed and their influences in terms of inductance, quality-factors, coupling coefficients and minimum insertion loss are evaluated through measurement and electromagnetic simulations. Results indicate that quality-factors are deteriorated by the use of patterned ground shields, whereas the use of floating shields allows a slight improvement without degrading other characteristics of the transformer.

Improving the quality factor of an RF spiral inductor with non-uniform metal width and non-uniform coil spacing

An improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor (Q factor). For this inductor layout, from outer coil to inner coil, the metal width is reduced by an arithmetic-progression step, while the metal spacing is increased by a geometric-progression step. An improved layout with variable width and changed spacing is of benefit to the Q factor of RF spiral inductor improvement (approximately 42.86%), mainly due to the suppression of eddy-current loss by weakening the current crowding effect in the center of the spiral inductor. In order to increase the Q factor further, for the novel inductor, a patterned ground shield is used with optimized layout together. The results indicate that, in the range of 0.5 to 16 GHz, the Q factor of the novel inductor is at an optimum, which improves by 67% more than conventional inductors with uniform geometry dimensions (equal width and equal spacing), is enhanced by nearly 23% more than a PGS inductor with uniform geometry dimensions, and improves by almost 20% more than an inductor with an improved layout.

Parameter Extraction and Optimal Design of Spiral Inductor Using Evolution Strategy and Sensitivity

For precise electromagnetic (EM) field simulation of the spiral inductor, electric conductivity of the inductor substrate is determined by evolution strategy to match the Taiwan Semiconductor Manufacturing Company (TSMC) process. Based on this parameter, patterned ground shield (PGS) of an on-chip spiral inductor is designed using deterministic optimization method. The design parameters are lengths and widths of ground strips and widths of slots. For sensitivity analysis, approximate adjoint variable method is used. Significant increase in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -factor is observed in final design while reduction of inductance is minimal. Spiral inductor with optimized PGS is used in input matching circuit of 2.45-GHz low noise amplifier (LNA), which shows improved noise figure characteristics compared to non-PGS case.

On-Die Synthesized Inductors: Boon or Bane?

Spiral inductor Q factor increases with increasing intermetal dielectric and/or metal winding thicknesses and substrate resistivity. The peak Q also increases with decreasing inductance, showing a clear advantage in chip area and Q for sub-nH inductance values-which becomes practical at frequencies in the mm-wave range. As previously described, substrate parasitics absorb less energy when the spiral is driven differentially, giving almost 2x improvement in peak-Q. The BiCMOS inductors are realized in first and second metals only, with a patterned ground shield (not floating). The peak-Q of the 0.1nH inductor in BiCMOS lies in the 60 GHz band. The stacked metal CMOS-SOI inductors (i.e., all interconnect metals in parallel) realize comparable performance without the thick metal option, due to decreased losses of the semi-insulating SOI substrate. Active inductors are used in specific situations such as peaking the response of RF amplifiers in LO chains, where dynamic range is less critical and a considerable savings in IC area may be realized compared to passive peaking coils.

Design of SIPC‐based complementary LC‐QVCO in 0.18‐μm CMOS technology for WiMAX application

PurposeThe purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.Design/methodology/approachA pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).FindingsA quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm2 of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.Research limitations/implicationsOwing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.Practical implicationsThe designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.Originality/valueThis paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.

Substrate Noise Coupling Reduction in $LC$ Voltage-Controlled Oscillators

In this letter, a substrate noise coupling effect in LC voltage-controlled oscillators (VCOs) was investigated. By 0.18-mum CMOS technology, three 2.4-GHz VCOs were designed using different types of spiral inductors to observe the substrate noise induced spurs. Compared with the design using a standard inductor, the proposed deep N-well (DNW) and patterned ground shield (PGS) VCOs demonstrated clearly reduced third-order intermodulation spurs by 6-8 and 10-15 dB, respectively. Based on the established physical-based equivalent circuit models, we found that the low-impedance paths introduced by DNW and PGS were the dominant factor for the observed substrate noise reduction in the proposed VCOs.

Design of high-performance compact CMOS distributed amplifiers with on-chip patterned ground shield inductors

A CMOS distributed amplifier incorporating on-chip patterned ground shield (PGS) spiral inductors has been developed using a standard low-cost 0.25 µm CMOS process. Measured results show that this distributed amplifier has an average gain of 7 dB, return loss of more than 10 dB, and noise figure between 4.1–6.1 dB across DC 11 GHz. The amplifier occupies a small chip area of only 1.2×0.8 mm2, including RF pads. These represent the best results for 0.25 µm CMOS distributed amplifiers and demonstrate that miniaturisation and high performance can be achieved for CMOS distributed amplifiers and other wideband RFICs by implementing on-chip PGS inductors.

A Study of On-Chip Stacked Multiloop Spiral Inductors

This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partial-element equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency-dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.

Pattern Density Effect on Characteristics of Spiral Inductor with Patterned Ground Shield

In this paper, we describe the pattern density effect on the characteristics of a spiral inductor with a patterned ground shield (PGS) fabricated using complementary metal–oxide–semiconductor (CMOS) technology. The inductance of the inductor is nearly constant for various pattern densities owing to the constant magnetic energy of the electromagnetic wave stored in the inductor. The quality factor of the inductor at a substrate resistivity ≥ 10 Ω·cm is maximum at a pattern density where the energy loss in the inductor is minimum because the energy loss in the silicon substrate decreases and the energy loss in the PGS increases as pattern density increases. In contrast, the quality factor of the inductor at a substrate resistivity of 10 mΩ·cm slightly decreases as pattern density increases owing to a slight increase in the energy loss in the inductor.

2.4 GHz ISM-Band Receiver Design in a 0.18 $\mu{\hbox{m}}$ Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm2.

Corrections on "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes"

Corrections on "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes"

RF 집적회로를 위한 0.18 μm CMOS 표준 디지털 공정 기반 인덕터 라이브러리

본 논문에서는 표준 디지털 0.18 <TEX>${\mu}m$</TEX> CMOS 공정을 기반으로 하는 RF 집적회로 설계를 위해 인덕터 라이브러리를 개발하였다. 개발된 인덕터 라이브러리에는 일반적인 표준(standard) 구조의 인덕터를 비롯하여, PGS(Patterned Ground Shield)를 적용하여 Q 지수를 향상시킨 인덕터, 금속선의 직렬 저항을 줄임으로써 Q 지수를 향상시킨 다층금속선(multilayer) 인덕터, 같은 면적에서 높은 인덕턴스 구현에 유리한 적층형(stacked) 인덕터 등을 포함한다. 본 논문에서는 각 인덕터 구조에 대하여 측정 결과와 3차원 전자기파 시뮬레이션 결과를 바탕으로 한 특성 해석 및 비교 분석을 하였고, 각 구조에 대한 등가회로 모델 확립 및 추출 과정도 연구하였다. 본 연구의 결과를 바탕으로 여러 설계 요구 사항을 만족시키는 최적의 인덕터 설계가 가능해졌으며 표준 CMOS 공정을 이용하는 저가의 RF 집적회로 개발이 가능해진다. An inductor library for efficient low cost RFIC design has been developed based on a standard digital 0.18 <TEX>${\mu}m$</TEX> CMOS process. The developed library provides four structural variations that are most popular in RFIC design; standard spiral structure, patterned ground shield(PGS) structure to enhance quality factor, stacked structure to enable high inductance values in a given silicon area, multilayer structure to lower series resistance. Electromagnetic simulation, equivalent circuit, and parameter extraction processes have been verified based on measurement results. The extensive measurement and simulation results of the inductor library can be a great asset for low cost RFIC design and development.

Characterization and modeling of silicon integrated spiral inductors for high-frequency applications

This paper presents the characterization and modeling of 0.3- to 0.8-nH radial patterned ground shield circular inductors fabricated in a silicon bipolar technology for RF applications. An extensive validation of measurement accuracy is first addressed taking into account both calibration and de-embedding issues. A novel five-step de-embedding technique is also proposed to improve the accuracy of small inductor measurements. The accuracy of de-embedded experimental data in the range 0.3-0.8 nH is demonstrated by comparing the measured low-frequency inductance with electromagnetic simulations of a large set of inductors. Based on both electromagnetic simulations and experimental measurements, the well-known current sheet expression for circular spirals is revised and modified to improve its accuracy at lower inductance values. The proposed expression is also extended to inductors with polygonal geometries showing significant improvements with respect to the state-of-the-art. Finally, the original and modified expressions are employed in a lumped scalable model for silicon spiral inductors. Comparisons with measured data revealed that the modified expression allows error reductions as large as 20% with respect to the original one, on both inductance and quality factor simulations.

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy

An Analytical Model of Electric Substrate Losses for Planar Spiral Inductors on Silicon

This paper presents a physically based model for estimating the substrate losses due to electric field penetration for planar spiral inductors on silicon not using patterned ground shield. The model, which does not use any fitting parameter, shows excellent agreement with measured data. It has been tested across a variety of inductor geometries and two different substrates up to 10 GHz

Frequency-Thermal Characterization of On-Chip Transformers With Patterned Ground Shields

Extensive studies on the performance of on-chip CMOS transformers with and without patterned ground shields (PGSs) at different temperatures are carried out in this paper. These transformers are fabricated using 0.18-mum RF CMOS processes and are designed to have either interleaved or center-tapped interleaved geometries, respectively, but with the same inner dimensions, metal track widths, track spacings, and silicon substrate. Based on the two-port S-parameters measured at different temperatures, all performance parameters of these transformers, such as frequency- and temperature-dependent maximum available gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ), quality factor (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) of the primary or secondary coil, and power loss (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">loss</sub> ) are characterized and compared. It is found that: 1) the values of the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> and Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> factor usually decrease with the temperature; however, there may be reverse temperature effects on both G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> and Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> factor beyond certain frequency; 2) with the same geometric parameters, interleaved transformers exhibit better low-frequency performance than center-tapped interleaved transformers, whereas the center-tapped configurations possess lower values of NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> at higher frequencies; and 3) with temperature rising, the degradation in performance of the interleaved transformers can be effectively compensated by the implementation of a PGS, while for center-tapped geometry, the shielding effectiveness of PGS on the performance improvement is ineffective

Characterization and Modeling of Pattern Ground Shield and Silicon-Substrate Effects on Radio-Frequency Monolithic Bifilar Transformers for Ultra-Wide Band Radio-Frequency Integrated Circuit Applications

In this paper, an analysis of the effects of pattern-ground-shield (PGS) and silicon-substrate on the performances of RF monolithic bifilar transformers are demonstrated. It was found that high-quality-factor and low-power-loss transformers can be obtained if the optimized PGS (OPGS) of polysilicon is adopted and the complementary metal–oxide–semiconductor (CMOS)-process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS (CPGS), which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 253.6% (from 3.79 to 13.4) increase in Q-factor, a 14% (from 0.7 to 0.798) increase in magnetic-coupling factor (kIm), a 51.1% (from 0.55 to 0.831) increase in maximum available power gain (GAmax), and a 1.79 dB (from 2.597 to 0.807) reduction in minimum noise factor (NFmin) were achieved at 8 GHz for a bifilar transformer with an overall dimension of 230×215 µm2.

High-Performance On-Chip Transformers With Partial Polysilicon Patterned Ground Shields (PGS)

In this brief, we propose the concept of patterned ground shields (PGSs) to improve the performances of RF passive devices, such as inductors and transformers. Partial PGS can be achieved after the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of an RF passive device, is removed for the purpose of reducing the large parasitic capacitance. A set of test transformers has been implemented to demonstrate the partial PGS. The results show that when the partial PGS was adopted, a 56.5% (from 6.12 to 9.58) and a 55.7% (from 5.55 to 8.64) increase in Q-factor, an 18.2% (from 0.67 to 0.79) and a 21.4% (from 0.66 to 0.8) increase in maximum available power gain (GAmax), and an 18.4% (from 0.69 to 0.82) and a 21.2% (from 0.69 to 0.83) increase in magnetic-coupling factor (kim) were achieved at 4.2 and 5.2 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum2. Furthermore, compared with the transformer with traditional PGS, a 9.9% (from 10.1 to 11.1 GHz) increase in resonant frequency (fSR), a 38% (from 6.94 to 9.58) increase in Q-factor at 4.2 GHz, and a 5.3% (from 0.75 to 0.79) increase in GAmax at 4.2 GHz were obtained. These results demonstrate that the proposed partial PGS is very promising for high-performance RF-ICs applications

High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW