Abstract
Spiral inductor Q factor increases with increasing intermetal dielectric and/or metal winding thicknesses and substrate resistivity. The peak Q also increases with decreasing inductance, showing a clear advantage in chip area and Q for sub-nH inductance values-which becomes practical at frequencies in the mm-wave range. As previously described, substrate parasitics absorb less energy when the spiral is driven differentially, giving almost 2x improvement in peak-Q. The BiCMOS inductors are realized in first and second metals only, with a patterned ground shield (not floating). The peak-Q of the 0.1nH inductor in BiCMOS lies in the 60 GHz band. The stacked metal CMOS-SOI inductors (i.e., all interconnect metals in parallel) realize comparable performance without the thick metal option, due to decreased losses of the semi-insulating SOI substrate. Active inductors are used in specific situations such as peaking the response of RF amplifiers in LO chains, where dynamic range is less critical and a considerable savings in IC area may be realized compared to passive peaking coils.
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