Parasitic Leakage Research Articles

Numerical Investigation of Abradable Coating Removal in Aircraft Engines Through Plastic Constitutive Law

Abstract In the field of turbomachines, better engine performances are achieved by reducing possible parasitic leakage flows through the closure of the clearance distance between blade tips and surrounding stationary casings and direct structural contact is now considered as part of the normal life of aircraft engines. In order to avoid catastrophic scenarios due to direct tip incursions into a bare metal housing, implementation of abradable coatings has been widely recognized as a robust solution offering several advantages: reducing potential nonrepairable damage to the incurring blade as well as adjusting operating clearances, in situ, to accept physical contact events. Nevertheless, the knowledge on the process of material removal affecting abradable coatings is very limited and it seems urgent to develop dedicated predicting numerical tools. The present work introduces a macroscopic model of the material removal through a piecewise linear plastic constitutive law which allows for real time access to the current abradable liner profile within a time-stepping approach of the explicit family. In order to reduce computational loads, the original finite element formulation of the blade of interest is projected onto a reduced-order basis embedding centrifugal stiffening. First results prove convergence in time and space and show that the frequency content of the blade response is clearly sensitive to the presence of abradable material. The continuous opening of the clearance between the blade tip and the casing due to the material removal yields larger amplitudes of motion and new scenarios of structural divergence far from the usual linear conditions provided by the well-known Campbell diagrams.

Cascade Organic Solar Cells

We demonstrate planar organic solar cells consisting of a series of complementary donor materials with cascading exciton energies, incorporated in the following structure: glass/indium-tin-oxide/donor cascade/C60/bathocuproine/Al. Using a tetracene layer grown in a descending energy cascade on 5,6-diphenyl-tetracene and capped with 5,6,11,12-tetraphenyl-tetracene, where the accessibility of the π-system in each material is expected to influence the rate of parasitic carrier leakage and charge recombination at the donor/acceptor interface, we observe an increase in open circuit voltage (Voc) of approximately 40% (corresponding to a change of +200 mV) compared to that of a single tetracene donor. Little change is observed in other parameters such as fill factor and short circuit current density (FF = 0.50 ± 0.02 and Jsc = 2.55 ± 0.23 mA/cm2) compared to those of the control tetracene–C60 solar cells (FF = 0.54 ± 0.02 and Jsc = 2.86 ± 0.23 mA/cm2). We demonstrate that this cascade architecture is effective i...

Tunneling component suppression in charge pumping measurement and reliability study for high- k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high- k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high- k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO 2-dominated high- k gate dielectrics is like mobile defect; while that with SiO 2-dominated ones is similar to the near-interface/border trap.

Failure Analysis and Radiation-Enabled Circuit Simulation of a Dual Charge Pump Circuit

Dual charge pump data show a reduction of circuit output voltage with dose. Through testing of individual process monitors, the response is identified as parasitic interdevice leakage caused by trapped oxide charge buildup in the isolation oxide. A library of compact models is generated for the field oxide parasitic based on test structure data along with 2-D structure simulation results. The charge pump schematic is then back annotated with transistors representative of the parasitic at different dose levels. Inclusion of the parasitic devices in schematic allows for simulation of the entire circuit at a specific dose. The reduction of circuit output with dose is then re-created in simulation.

Polymer space-charge-limited transistor as a solid-state vacuum tube triode

We report the construction of a polymer space-charge-limited transistor (SCLT), a solid-state version of vacuum tube triode. The SCLT achieves a high on/off ratio of 3×105 at a low operation voltage of 1.5 V by using high quality insulators both above and below the grid base electrode. Applying a greater bias to the base increases the barrier potential, and turns off the channel current, without introducing a large parasitic leakage current. Simulation result verifies the influence of base bias on channel potential distribution. The output current density is 1.7 mA/cm2 with current gain greater than 1000.

GaN photovoltaic leakage current and correlation to grain size

GaN p-i-n solar PV structures grown by rf plasma assisted molecular beam epitaxy (MBE) produce high performance IV characteristics with a leakage current density of less than 1×10−4 mA cm−2 at 0.1 V forward bias and an on-resistance of 0.039 Ω cm2. Leakage current measurements taken for different size diodes processed on the same sample containing the solar cells reveal that current density increases with diode area, indicating that leakage is not a large function of surface leakage along the mesa. Nonannealed Pt/Au Ohmic p-contacts produce a contact resistivity of 4.91×10−4 Ω cm−2 for thin Mg doped contact layers with sheet resistivity of 62196 Ω/◻. Under concentrated sunlight the cells produce an open-circuit voltage of 2.5 V and short circuit currents as high as 30 mA cm−2. Multiple growths comprised the study and on each wafer the IV curves representing several diodes showed considerable variation in parasitic leakage current density at low voltages on some wafers and practically no variation on others. It appears that a smaller grain size within the GaN thin film accounts for higher levels of dark current.

InAlN/GaN heterostructure field-effect transistors on Fe-doped semi-insulating GaN substrates

InAlN/GaN heterostructure field-effect transistors (HFETs) have been grown and fabricated on Fe-doped semi-insulating c-plane GaN substrates. The problematic parasitic leakage caused by interface charge between the epitaxial layers and the GaN substrate as well as any adverse effect of the substrate surface damage caused by the mechanical chemical polish employed on the substrates has been circumvented by using a combination of inductively coupled plasma dry etching and in situ H2 etching. As a result, the current leakage for 100 μm separation mesa-to-mesa was reduced down to 3×10−9 A/mm at 10 V voltage bias for a 320 μm mesa pad width normal to the current flow direction and the corresponding GaN buffer resistivity was about 3.5×108 Ω cm. Owing to the good thermal conductivity of GaN substrates, the HFETs exhibit much less current degradation, compared to those on a sapphire substrate, at high drain biases. Likewise, the dc and pulsed I-V characteristics were reasonably similar, suggestive of negligible drain current lag. A dc saturation drain current density of 1.0 A/mm was achieved at zero gate bias. For HFETs with 1.1 μm gate length and 90 μm gate width, the maximum extrinsic dc transconductance was 275 mS/mm.

Enhanced P3HT OTFT Transport Performance Using Double Gate Modulation Scheme

Electrical properties of single-gated (bottom-gated or top-gated) and double-gated (DG) organic thin-film transistors (OTFTs) are systematically investigated in terms of threshold voltage (V th), subthreshold slope, and I ON/OFF. We found that the device structure has significant impacts on the aforementioned electrical properties and the operation modes in a poly-3-hexyl thiophene DG OTFT. An empirical electrostatic potential model is employed to describe well V th behaviors of DG OTFTs in different modulation schemes. In addition, selective active-area coating in OTFTs is realized using an inkjet printing process, and consequently, parasitic leakage is much suppressed.

186 K operation of terahertz quantum-cascade lasers based on a diagonal design

Resonant-phonon terahertz quantum-cascade lasers operating up to a heat-sink temperature of 186 K are demonstrated. This record temperature performance is achieved based on a diagonal design, with the objective to increase the upper-state lifetime and therefore the gain at elevated temperatures. The increased diagonality also lowers the operating current densities by limiting the flow of parasitic leakage current. Quantitatively, the diagonality is characterized by a radiative oscillator strength that is smaller by a factor of two from the least of any previously published designs. At the lasing frequency of 3.9 THz, 63 mW of peak optical power was measured at 5 K, and approximately 5 mW could still be detected at 180 K.

Direct Patterning of Organic‐Thin‐Film‐Transistor Arrays via a “Dry‐Taping” Approach

Dry patterning of a variety of solution- and vapor-deposited small-molecule organic semiconductors using adhesive tape is demonstrated. This technique allows direct fabrication of large-area arrays of bottom-contact high-performance organic- thin-film field-effect transistors with self-aligned electrodes. These patterned devices exhibit significantly higher on/off ratios and lower parasitic leakage currents than control unpatterned devices of the same materials.

Improved GeOI substrates for pMOSFET off-state leakage control

The origin of parasitic leakage that occurs in some GeOI pMOSFETs has been investigated and located at the Ge-buried oxide (BOX) interface. Silicon passivation of that interface was found to be effective in reducing this current. An optimum thickness of the buried silicon capping is required to reduce the parasitic leakage current while preserving Ge-like back channel transport properties.

MBE GROWTH AND CHARACTERIZATION OF Mg-DOPED III-NITRIDES ON SAPPHIRE

Plasma-assisted molecular beam epitaxial growth of Mg -doped GaN and InGaN on a sapphire substrate is investigated in this study. Electrical characteristics of p -type GaN strongly depend on the flux of Mg acceptors and the growth temperature. Only the intermediate range of Mg fluxes (beam equivalent pressures near 1×10-9T) produce p -type GaN with good electrical properties, and a maximum hole concentration of 3.5 × 1018 cm-3 is obtained with a Hall mobility of 2.1 cm2/V·s. Due to the strong surface accumulation of electrons, Hall measurements do not indicate p -type polarity for In fraction beyond 11%. In contrast, hot probe measurements show that p -polarity can be measured for the entire range of Mg -doped In mole fractions. Electroluminescence also indicates p -polarity for Ga -rich mole fractions. In x Ga1- x N p - n homojunctions are fabricated and tested. All GaN devices show low series resistance (0.03 ohm-cm2) and insignificant parasitic leakage. IV curves of all three InGaN homojunctions show rectifying characteristics under dark conditions and photo-response under outdoor sunlight, indicating the existence of holes in InGaN with up to 40% In content.

A Novel Biasing Technique for Addressable Parametric Arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence.

Multiphase Transformer Effect and Harmonic Response Analysis of Accelerator Power System

Accelerator main dipole magnet system magnetic field regulation depends on its transmission line characteristic properties and its power supply system regulations. In addition, the main magnet AC power transformer configuration has indirect impact on the field quality of dipole magnet. A large accelerator main magnet system consists of hundreds, even thousands, of dipole magnets. They are linked together under selected configurations to provide uniform dipole fields when powered. When all dipole magnets are linked together in a synchrotron, they become a coupled pair of very high order complex ladder networks due to magnet parasitic capacitance, leakage resistance, and conductor resistance. In this study, we present multiphase transformer effect and harmonic response analysis of AGS main magnet system.

Growth, fabrication, and characterization of InGaN solar cells

AbstractThe InGaN alloy system offers a unique opportunity to develop high efficiency multi‐junction solar cells. In this study, single junction solar cells made of Inx Ga1–x N are successfully developed, with x = 0, 0.2, and 0.3. The materials are grown on sapphire substrates by MBE, consisting of a Si‐doped InGaN layer, an intrinsic layer and an Mg‐doped InGaN layer on the top. The I –V curves indicate that the cell made of all‐GaN has low series resistance (0.12 Ω cm2) and insignificant parasitic leakage. Contact resistances of p and n contacts are 2.9 × 10–2 Ω cm2 and 2.0 × 10–3 Ω cm2, respectively. Upon illumination by a 200 mW/cm2, 325 nm laser, Voc is measured at 2.5 V with a fill factor of 61%. Clear photo‐responses are also observed in both InGaN cells with 0.2 and 0.3 Indium content when illuminated by outdoor sunlight. But it is difficult to determine the solar performance due to the large leakage current, which may be caused by the material defects. A thicker buffer layer or GaN template can be applied to the future growth process to reduce the defect density of InGaN films. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Total Ionizing Dose Hardness Assurance Issues for High Dose Rate Environments

Transistors and ICs were irradiated at dose rates from 0.2 to 2times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple ldquoovertestsrdquo at dose rates from 50 to 300 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )/s environments is to use radiation sources that mimic the system environment.

Large-area patterning of a solution-processable organic semiconductor to reduce parasitic leakage and off currents in thin-film transistors

We describe two techniques for patterning spin-cast thin films of a solution-processable organic semiconductor, triethylsilylethylnyl anthradithiophene (TES ADT), to eliminate parasitic leakage currents and to lower off currents in thin-film transistors. One technique utilizes UV light in the presence of solvent vapors to simultaneously define the active channel and to crystallize TES ADT. The second technique selectively removes TES ADT from the nonchannel regions of the thin-film transistors through direct contact with a poly(dimethylsiloxane) stamp. Both patterning techniques yield thin-film transistors with high charge-carrier mobility (⩾0.1cm2∕Vs), low off currents (10−10–10−11A), and minimal parasitic leakage.

Origin and elimination method of parasitic gate leakage current for AlGaN/GaN heterostructure field effect transistor

The Schottky gate leakage current of AlGaN/GaN HFET was systematically investigated. Experimental results were acquired from gates of HFET and from round diodes on the same wafer. The performed analysis clearly shows that HFET gate current behaves according to additional physical mechanism. Hypothesis, that the source of parasitic leakage is the contact point between gate metal and two dimensional electron gas on the mesa edges, was theoretically and experimentally proved. Cost effective technological solution with SiO2 “patch” layer is presented. Transistors, manufactured with “patch” layer, have higher breakdown, two orders of magnitude lower gate leakage current, excellent performance and should be more reliable. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A New Technique for Measuring Gate-Oxide Leakage in Charging Protected MOSFETs

While accurate measurement of gate-oxide leakage in isolated CMOS oxides can be straightforward, it is not the case for CMOS oxides connected to a plasma-charging protection device. In this paper, a method enabling accurate gate-oxide leakage extraction from CMOS transistors directly connected to a gated MOSFET-based charging protection device is described. The method extracts gate-oxide leakage at the bottom side of the gate-oxide from the drain/source terminal of the protected MOSFETs biased into inversion while diverting the parasitic leakages from the protection device into a P+ tap sink. The location and design of the P+ tap sink play an important role on the success of the method. The method demonstrates a high measurement accuracy over the conventional method with a nearly 99% absorption efficiency of the protection-device-induced leakage by the P + tap sink, with the test structures used in this study. The method enables a saving of up to 30% of the layout space in the design of the charging test structures in test chips by eliminating usage of the fuse between the protected and protecting devices. A correlation study performed with the data measured by the new method and the conventional method suggests that both protected and protecting transistors can experience gate-oxide damage at the same time during back-end integrated circuit (IC) manufacturing process if the protected transistors violate the gate-charging design rules. It also indicates that the protected transistors have higher chance to receive more severe damage than the protecting transistors due to different oxide damage mechanisms associated with the terminal connectivity of these transistors

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.