Parasitic Bipolar Transistor Action Research Articles

Sub-10-nm Scalability of Emerging Nanowire Junctionless FETs Using a Schottky Metallic Core

Inefficient volume depletion is a dominant leakage mechanism in junctionless (JL) field-effect transistors (FET). Moreover, the realization of efficient volume depletion is compensated by the detrimental leakage mechanism of the lateral band-to-band tunneling (L-BTBT), which drastically degrades the performance of nanowire (NW) JLFETs with short gate lengths. A Schottky metallic core (SC) nanowire (NW) junctionless (JL) FET is therefore proposed herein to realize efficient volume depletion along with a significant reduction of the L-BTBT-induced parasitic leakage. Using calibrated three-dimensional (3-D) simulations, it is demonstrated that the presence of a Schottky metallic core effectively depletes the surrounding NW shell by abolishing the shielding effect of holes, which helps in realizing the efficient volume depletion that is desirable in OFF-state. Furthermore, it also leads to a significant reduction of the L-BTBT-induced parasitic bipolar junction transistor (BJT) action. This simultaneous suppression of both leakage mechanisms reduces the OFF-state current by around eight orders of magnitude, leading to a significant ON-state to OFF-state current (ION/IOFF) ratio of ~ 109 for a gate length of 20 nm. The reduced parasitic BJT action facilitates the scaling of SC NW JLFET, leading to a remarkable ION/IOFF ratio of ~ 107 even at a scaled gate length of 7 nm. The Schottky junction results in a vertical electric field that hinders the lateral electrostatic coupling of the drain field lines with the channel, leading to reduced detrimental short-channel effects in the sub-10-nm regime. This immunity against short-channel effects is further boosted by using high-k spacers. Thus, the excellent OFF-state behavior along with the reduced short-channel effects provides an incentive for realizing the proposed SC NW JLFET at sub-10-nm technology nodes.

Suppression of the Floating-Body Effect of Vertical-Cell DRAM With the Buried Body Engineering Method

Recently, new dynamic random-access memory (DRAM) structures have been used to sharply reduce chip size. One of these is vertical-cell DRAM that has the advantage of reducing the chip area by 33% compared with the conventional cell DRAM. However, since the bitline is made in Si trenches, it can cause a floating-body effect, which increases the OFF current. Here, we suggest the buried body engineering method as a simple way to deal with these disadvantages without changing the materials. This method significantly improved the electrical performance in comparison with the conventional buried contact. Especially, the OFF current, which is the most important factor influencing the refresh time, was dramatically reduced by a factor of 63. The reason for this dramatic decrease in the OFF current is that the holes accumulated in the body are removed immediately, and they do not generate a parasitic bipolar junction transistor (BJT) action. We also calculated the hole density using simulations and obtained the junction depth that suppresses the floating-body effect. Above all, we provide advanced insight into the mechanism of the parasitic BJT action due to the floating-body effect that occurs at the bottom contact region of vertical-cell DRAM.

Discharge Characteristics of a Triple-Well Diode-String ESD Clamp

In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.

A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

In this paper, we demonstrate a tunnel dielectric-based junctionless transistor, referred as TD JLT, which consists of a thin dielectric layer in the middle of the channel region of a JLT leading to a drastically reduced parasitic bipolar junction transistor (BJT) action. Using calibrated 2-D simulations, we show that the proposed TD JLT has a significantly low off-state leakage current due to the presence of a tunneling barrier, and an enhanced source-to-channel barrier height, which results in a diminished parasitic BJT action in the off-state. Further, the proposed TD JLT exhibits an extremely high $I_{{{ \mathrm{\scriptscriptstyle ON}}}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 1.1 \times 10^{{{\sf{ 7}}}}$ for a channel length of 20 nm and a significant( $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ ratio of $\sim 10^{{{\sf{ 2}}}}$ even for a channel length of 10 nm.

Physical Insights Into the Nature of Gate-Induced Drain Leakage in Ultrashort Channel Nanowire FETs

In this paper, we demonstrate that the lateral band-to-band tunneling component of gate-induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor (BJT) in the OFF-state (gate voltage = 0.0 V) of nanowire FETs (NW FETs). We discuss in detail the difference in the nature of GIDL, i.e., drain current dependence on the negative gate voltage ( ${V}_{\text {GS}} \le 0$ V) for different NW FET configurations. Furthermore, we show that the parasitic BJT action is significant in NW junctionless accumulation mode FET (JAMFET) and NW MOSFET in the OFF-state and diminishes as the gate voltage becomes negative. Using calibrated 3-D simulations, we investigate the impact of scaling on the NW FETs and show that the enhanced band gap due to the quantum confinement effect facilitates the scaling of the NW FETs to the sub-5-nm regime. In addition, we propose the use of a lightly doped drain extension to increase the ON-state to OFF-state current ratio ( ${I}_{ {{\scriptscriptstyle {ON}}}}/{I}_{ {\scriptscriptstyle {OFF}}})$ of NW JAMFET and NW MOSFET.

Nanotube Junctionless FET: Proposal, Design, and Investigation

In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high $I_{\mathrm{\scriptscriptstyle ON}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ratio of $\sim 10^{8}$ . Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping ( $N_{D} \geq 2 \times 10^{19}$ cm $^{-3}$ ) is due to a shielding effect initiated by the band-to-band tunneling.

Raised Source/Drain Dopingless Junctionless Accumulation Mode FET: Design and Analysis

We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced band-to-band tunneling-induced parasitic bipolar transistor action in the off-state as compared with the planar dopingless junctionless FET (DJFET) for sub-20-nm channel length devices. Further, the RDJAMFET has better gate control and shows significant improvements in terms of drain-induced barrier lowering, subthreshold swing, and $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ as compared with the DJFET for sub-20-nm channel length devices.

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture

In this paper, we propose the use of a p+ core in the core–shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral band-to-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) of $\sim 10^{7}$ even for a channel length of 7 nm.

On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device

In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.

Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor

We analyse a novel hybrid semiconductor field-effect transistor (FET), known as the junctionless tunnel FET (JL-TFET). We show that a parasitic bipolar transistor action, which is highly undesirable in conventional metal/oxide/semiconductor FETs and junctionless transistors, is the mechanism that activates the JL-TFET ON state. It is found that the sub-threshold slope (SS) in the JL-TFET is strongly dependent on the silicon thickness and a sub-60 mV/decade SS is observed for a thin silicon body only. We further study the JL-TFET design parameters as regards the effects of the control gate workfunction, P-gate workfunction, and isolation region on the JL-TFET characteristics.

Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance

In this brief, we propose a new extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> stepped gate (ESG) thin-film silicon-on-insulator laterally double-diffused metal-oxide-semiconductor (LDMOS) with an extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> - p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> junction instead of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p junction, thus delaying the parasitic bipolar junction transistor action. The stepped gate structure enhances RESURF in the drift region and minimizes the gate-drain capacitance. Based on 2-D simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed, and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate Structure

n- and p-channel poly-Si thin-film transistors with fully Ni-self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate structure (n- and p-channel FUSA-TFTs) have been successfully fabricated on a thick channel layer. The conventional poly-Si gate is replaced by the fully Ni-silicided gate, and the parasitic S/D resistance of the FUSA-TFTs is significantly reduced by the fully Ni-silicided S/D structure. The fully Ni-salicidation process is executed at a low temperature of for a short rapid thermal annealing time. Experimental results show that the FUSA-TFTs give increased on/off current ratio, improved subthreshold characteristics, less threshold voltage roll-off, lower parasitic S/D resistance, higher gate capacitance, and larger field-effect mobility than conventional TFTs. The FUSA-TFTs effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FUSA-TFTs are suitable for three-dimensional integration applications and high performance driver circuits in the active-matrix liquid crystal displays.

Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference

Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5 dB m of pulsed interference at frequencies of 1.23 GHz and 4 GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4 GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8 kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25 mA, respectively.

Modelling velocity saturation and kink effects in p-channel polysilicon thin-film transistors

Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.

The Impact of Deep Ni Salicidation and$hboxNH_3$Plasma Treatment on Nano-SOI FinFETs

In this letter, 50-nm gate-length nano-silicon-on-insulator FinFETs with deep Ni salicidation and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hboxNH_3$</tex> plasma treatment are fabricated. It is found that device performances, including subthreshold slope (SS) drain-induced barrier lowering (DIBL) and off-state leakage current, can be greatly improved by using deep Ni salicidation process compared to no Ni salicidation process. The deep Ni-salicided devices effectively suppress the floating-body effect and parasitic bipolar junction transistor action. In addition, the effect of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hboxNH_3$</tex> plasma on the deep Ni-salicided devices is discussed. Experimental results reveal that the devices under a new state-of-the-art <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hboxNH_3$</tex> plasma process can achieve better performance such as an SS of 66 mV/dec and a DIBL of 0.03 V.

High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure

In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.

Short channel effects in polysilicon thin film transistors

Short channel effects have been investigated in n-channel polysilicon thin film transistors. Transconductance degradation has been observed when reducing the channel length L and this effect has been explained with the presence of a parasitic resistance related to residual implant damage. Threshold voltage slighlty decreases for channel length around L=1 μm and simulations confirm that the roll-off of the threshold voltage is expected for L<1 μm. In the output characteristics a stronger kink effect has been observed at short L which, from a comprehensive analysis of the current components, can be attributed to an enhanced parasitic bipolar transistor action.

Kink effect in short-channel polycrystalline silicon thin-film transistors

Excess current, induced by impact ionization (kink effect) has been investigated in short-channel polysilicon thin-film transistors (TFTs). We have shown, both experimentally and by using two-dimensional (2-D) numerical simulations, that the output characteristics are substantially degraded by the kink effect as the channel length is reduced. In particular, we have shown that the excess current, triggered by the impact ionization and enhanced by the parasitic bipolar transistor action, scales nearly as L−2, thus making very difficult the downscaling of polysilicon TFTs. Such L dependence has been clarified through a detailed analysis of the current components obtained from 2-D numerical simulations. The analysis demonstrates that there are fundamental issues with the output characteristics, and it appears that the introduction of appropriate drain field relief structures will be necessary for the fabrication of short-channel polysilicon TFTs with high output impedance.