Abstract

In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.

Highlights

  • CMOS chips are vulnerable to electrostatic discharge (ESD) due to the thin gate oxides used, and protection devices are required at input pads

  • By analyzing the simulation results, we show that severe lattice heating in the diode device can occur due to a trigger of parasitic pnp bipolar transistor action

  • We encountered with an excessive lattice heating problem in the diode ESD protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs

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Summary

Introduction

CMOS chips are vulnerable to electrostatic discharge (ESD) due to the thin gate oxides used, and protection devices are required at input pads. In the diode input protection scheme, it is essential to include a VDD-VSS clamp NMOS device in an input pad structure to provide discharge paths for all possible human-body model (HBM) test modes. In RF ICs, to reduce parasitics added to input nodes, it is important to minimize the diode size by optimizing device structure. In this work, based on 2-D mixed-mode (device and circuit) simulation, we figure out that the mechanism leading to diode protection device failure is mostly related to a trigger of parasitic pnp bipolar transistor involving the p-type substrate contacts.

Diode ESD Protection Scheme and Protection Device Structures
Mixed-Mode Transient Simulations
Findings
Conclusions
Full Text
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