Parallel Prefix Adders Research Articles

Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications

This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

Design and Implementation of Braun Multiplier using Parallel Prefix Adders

In the recent trends of any application depends on delay and area consumption. The delay and area of consumption are the two important considerations of the industrial. These two parameters are considered for any industry application. This type of application can be developed by the different methods that are used in VLSI technology. The Braun multiplier was developed by two different methods. The CMOS and GDI methods are used to implement this multiplier. The parallel prefix adders are used in the multiplier. Braun multiplier is helpful for increasing the speed of the system. The Braun multiplier is designed in the Tanner V-13 EDA tool. The results of this type of multiplier were considered in both CMOS and GDI.

FLASH: Fast and Robust Framework for Privacy-preserving Machine Learning

Abstract Privacy-preserving machine learning (PPML) via Secure Multi-party Computation (MPC) has gained momentum in the recent past. Assuming a minimal network of pair-wise private channels, we propose an efficient four-party PPML framework over rings ℤ2ℓ, FLASH, the first of its kind in the regime of PPML framework, that achieves the strongest security notion of Guaranteed Output Delivery (all parties obtain the output irrespective of adversary’s behaviour). The state of the art ML frameworks such as ABY3 by Mohassel et.al (ACM CCS’18) and SecureNN by Wagh et.al (PETS’19) operate in the setting of 3 parties with one malicious corruption but achieve the weaker security guarantee of abort. We demonstrate PPML with real-time efficiency, using the following custom-made tools that overcome the limitations of the aforementioned state-of-the-art– (a) dot product, which is independent of the vector size unlike the state-of-the-art ABY3, SecureNN and ASTRA by Chaudhari et.al (ACM CCSW’19), all of which have linear dependence on the vector size. (b) Truncation and MSB Extraction, which are constant round and free of circuits like Parallel Prefix Adder (PPA) and Ripple Carry Adder (RCA), unlike ABY3 which uses these circuits and has round complexity of the order of depth of these circuits. We then exhibit the application of our FLASH framework in the secure server-aided prediction of vital algorithms– Linear Regression, Logistic Regression, Deep Neural Networks, and Binarized Neural Networks. We substantiate our theoretical claims through improvement in benchmarks of the aforementioned algorithms when compared with the current best framework ABY3. All the protocols are implemented over a 64-bit ring in LAN and WAN. Our experiments demonstrate that, for MNIST dataset, the improvement (in terms of throughput) ranges from 24 × to 1390 × over LAN and WAN together.

Повышение эффективности работы многоразрядного двоичного параллельно-префиксного сумматора

Повышение эффективности работы многоразрядного двоичного параллельно-префиксного сумматора

Architecture of 2X2 FIR Filter using Vedic Multiplier and Brent-Kung Adder

This paper proposed, a 2X2 FIR filter which is based on the Brent-Kung adder and Vedic multiplier. A 2X2 FIR filter has been designed using Brent-Kung-Adder (BKA) and filter coefficient. Verilog platform and Xilinx 14.5 software. The Brent- Kung adder is much faster than the look ahead carry adder (LACD), carry select adder and ripple carry adder (RCA) and it is a parallel prefix adder. Lowarea and the power consumption in Brent-kung adder is also less as compared to various adders. Multiplication of a number using the Vedic multiplier is arithmetic key operation to be performed with low power consumption of and increase the speed in the consequence applications. Proposed design utilize the common multiplication in cross multiply to compensate the problem of delay which is occurring in the Booth Multiplier and Array Multiplier and etc. Brent-kung adder used to decrease the delay which was occur in the multiplier and significantly reduce the quantity of logic elements such as gates, signals etc.

Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1},2^{n}+2^{n-1}-1,2^{n+1}-1\}$

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set ${\tau }=\{{2}^{{{n}}}{-1,}{2}^{{{n}}},\,\,2^{{{n}}}+1\}$ , with nearly ${2}^{3n}$ dynamic range and fast parallel-prefix adders. However, the ${2}^{{{n}}}+1$ channel is ${4}{\Delta }{{G}}$ slower ( ${\Delta }{{G}} =$ simple 2-input gate delay). To remedy such speed imbalance and accommodate higher dynamic ranges, other moduli forms have joined $\{{2}^{{{n}}},{2}^{{{n}}}-1\}$ , with only slightly slower adders (e.g., ${2}^{{{n}+1}}{-1} (n={2}^{{\text {h}}}){,}{2}^{{{n}}}{-}{2}^{q}{-1({q} , and ${2}^{{{n}}}{-3}$ , with at most ${2\Delta {G}}$ more parallel-prefix delay). However, the more the number of moduli, the harder and more costly becomes the required reverse convertor, while otherwise increasing the channel widths ${n}$ may incur some speed loss. Nevertheless, in the present work, the 3-moduli set ${\tau }^{+}=\{{2}^{{{n}+1}}{,}{2}^{{{n}}}{+}{2}^{n-1}{-1,} {2}^{{{n}+1}}{-1}\}$ is presented, with almost $6\times $ dynamic range than that of the aforementioned $\tau $ , where the corresponding parallel-prefix adders are as fast as those for the ${2}^{{{n}}}$ and ${2}^{{{n}}}{-1}$ channels. The required nontrivial forward convertor for modulo ${2}^{{{n}}}+{2}^{{{n}-1}}{-1}$ and the reverse convertor for the new 3-moduli set are also designed. Moreover, a new 3-input parallel-prefix node is designed and incorporated, as appropriate for ${n}= 2^{\text {h}}$ , within the employed parallel-prefix networks with the overall advantage of $2\Delta {G}$ speed-up. Improvements of proposed designs are confirmed via circuit synthesis.

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder

Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation

This article presents hierarchical single compound adder-based MAC with assertion based error correction for speculation variations in the prefix addition for FIR filter design. The VLSI implementation of approximation in prefix adder results show a significant delay and complexity reductions, all this at the cost of latency measures when speculation fails during carry propagation, which is the main reason preventing the use of speculation in parallel-prefix adders in DSP applications. The speculative adder which is based on Han Carlson parallel prefix adder structure accomplishes better reduction in latency. Introducing a structured and efficient shift-add technique and explore latency reduction by incorporating approximation in addition. The improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware. Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed.

Design and implementation of area efficient EAIC modulo adder

The addition of binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Binary adders are the crucial building blocks in very large-scale integrated (VLSI) circuits. Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. In this paper, modified End-Around Inverted Carry (EAIC) area-efficient modulo adder is designed using various parallel prefix adders. In the proposed design, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Compared with the same type of modulo adder structure, the proposed designs offer reduced area and delay reduced compared to the existing design.

Enhancement and Usage of Different Sorts of Efficient Parallel Prefix Adders

Portray Mighty exploit adders (aside unfamiliar pretence as invite apparatus or against introduce adders) are track to crack the stroke in VLSI designs. In provincial case, this ordinance statement does howl decrypt right away into FPGA implementations befitting to chains on assertion arena configurations and routing overhead. This version preparation investigates span forms of Stand-machinery adders (Spanning tree adder and Brent-kung adder, the Kogge-Stone) and associates them to the uncomplicated a Carry Skip Adder (CSA) Ripple Carry Adder(RCA). The deception parameters steady for the comparative division of the presented adders are: the amid of logic gates, crawl run in plagiarized at the drop of a hat clog modeling in Xilinx curtailment. As a expectation, this instant affectation of alternate adders, Kogge-Stone adder and ready-made PPA effort akin to crisis slow.

Design and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based

Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information.

New energy‐efficient hybrid wide‐operand adder architecture

The consumer electronics markets have increased the demand for high-speed and low-power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel-prefix adders, exhibit high-power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade-off between the delay and power-consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel-prefix adders the least-significant carries are produced much sooner than the most-significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least-significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least-significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65-nm-TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area-delay-product in comparison with state-of-the-art wide-operand adders.

Design a High Speed Multiplier using Two Phase PPA

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

Performance Evaluation of New Adder Designed for Electronic Circuits

Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.

Delay Efficient Vedic Multiplier for DSP

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

Efficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers

In this study, low-cost and high-throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 2 8 . In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimised combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.

Design of High Speed Advanced Encryption Standard using PPA and PPM

Basically, internet security plays crucial role in past three decades. So in worldwide Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. In this paper we proposed the simplified AES algorithm (S-DES) using parallel prefix adder (PPA) and parallel prefix multiplier (PPM). This parallel prefix adder and parallel prefix multiplier will generate a product formed by multiplying the multiplicand. This algorithm possess specific structure to encrypt and decrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, substitution, improvement and change encoding strategies. At last the key extension module will comprise the quantity of iterative preparing rounds so as to expand its resistance against unapproved assaults.

Low Power High Speed Arithmetic Circuits

In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

A Comprehensive Comparative Analysis of Parallel Prefix Adders for ASIC Implementation

Parallel Prefix Adders are the most common choice for fast adders. The design of efficient adder is always a compromise between the parameters such as area and delay. This paper discuss the comparison and performance analysis of different parallel prefix adders on the basis of these performance parameters, and thereby providing an option for selecting the most appropriate adder topology for ASIC implementations. The tree adder topologies considered in this work are Kogge- Stone, Ladner-Fischer, Brent-Kung and Sklansky adders. The comparison is performed for bit widths ranging from 16 bits to 1024 bits. Along with the comparison of conventional tree adders, an attempt is made to study the effect of sectioning of the data into different blocks, and thus performing additions at section level and cascading them as in a ripple carry adder. Over the complete range from 16 bits to 1024 bits, Kogge-Stone adder has the best delay performance and Brent- Kung adder has the best performance (excluding RCA) in terms of area and power. Kogge-Stone adder has the minimum area-delay product for small values of N, while for medium to large values of N (up to 1024 bits), Brent-Kung adder show minimum value.