Abstract
In the recent trends of any application depends on delay and area consumption. The delay and area of consumption are the two important considerations of the industrial. These two parameters are considered for any industry application. This type of application can be developed by the different methods that are used in VLSI technology. The Braun multiplier was developed by two different methods. The CMOS and GDI methods are used to implement this multiplier. The parallel prefix adders are used in the multiplier. Braun multiplier is helpful for increasing the speed of the system. The Braun multiplier is designed in the Tanner V-13 EDA tool. The results of this type of multiplier were considered in both CMOS and GDI.
Highlights
The Braun multiplier is designed in the Tanner V-13 EDA tool. The results of this type of multiplier were considered in both CMOS and GDI
The performance of the any system in digital environmental can be improved by the CMOS technology
When we compare CMOS technology there is another method that was consider for the design that is GDI method
Summary
The arithmetic operation is performed with help of the multiplication. The multiplication can be defined by multiplier. The main purpose of going with GDI is having less transistors count This affect on the size of the system and power dissipation of the system is reduced. The implementation of the Braun multiplier consists of C-S adders, No of AND gates and one R-C Adder These types of multipliers having the glitching problem. Implementation of Braun multiplier using B-K adders: This structure is used to increase the speed and reduce the delay of the system. The delay of the Braun multiplier is compared in both CMOS and GDI methods. The implementation of the K-S adder with the Braun multiplier shown in figure
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