Design and implementation of area efficient EAIC modulo adder

Abstract

The addition of binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Binary adders are the crucial building blocks in very large-scale integrated (VLSI) circuits. Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. In this paper, modified End-Around Inverted Carry (EAIC) area-efficient modulo adder is designed using various parallel prefix adders. In the proposed design, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Compared with the same type of modulo adder structure, the proposed designs offer reduced area and delay reduced compared to the existing design.