Memory Parallel Research Articles

Bioinspired and Low-Power 2D Machine Vision with Adaptive Machine Learning and Forgetting.

Natural intelligence has many dimensions, with some of its most important manifestations being tied to learning about the environment and making behavioral changes. In primates, vision plays a critical role in learning. The underlying biological neural networks contain specialized neurons and synapses which not only sense and process visual stimuli but also learn and adapt with remarkable energy efficiency. Forgetting also plays an active role in learning. Mimicking the adaptive neurobiological mechanisms for seeing, learning, and forgetting can, therefore, accelerate the development of artificial intelligence (AI) and bridge the massive energy gap that exists between AI and biological intelligence. Here, we demonstrate a bioinspired machine vision system based on a 2D phototransistor array fabricated from large-area monolayer molybdenum disulfide (MoS2) and integrated with an analog, nonvolatile, and programmable memory gate-stack; this architecture not only enables dynamic learning and relearning from visual stimuli but also offers learning adaptability under noisy illumination conditions at miniscule energy expenditure. In short, our demonstrated "all-in-one" hardware vision platform combines "sensing", "computing", and "storage" to not only overcome the von Neumann bottleneck of conventional complementary metal-oxide-semiconductor (CMOS) technology but also to eliminate the need for peripheral circuits and sensors.

Analog Tunnel Memory Based on Programmable Metallization for Passive Neuromorphic Circuits.

Although experimental implementations of memristive crossbar arrays have indicated the potential of these networks for in-memory computing, their performance is generally limited by an intrinsic variability on the device level as a result of the stochastic formation of conducting filaments. A tunnel-type memristive device typically exhibits small switching variations, owing to the relatively uniform interface effect. However, the low mobility of oxygen ions and large depolarization field result in slow operation speed and poor retention. Here, we demonstrate a quantum-tunneling memory with Ag-doped percolating systems, which possesses desired characteristics for large-scale artificial neural networks. The percolating layer suppresses the random formation of conductive filaments, and the nonvolatile modulation of the Fowler-Nordheim tunneling current is enabled by the collective movement of active Ag nanocrystals with high mobility and a minimal depolarization field. Such devices simultaneously possess electroforming-free characteristics, record low switching variabilities (temporal and spatial variation down to 1.6 and 2.1%, respectively), nanosecond operation speed, and long data retention (>104 s at 85 °C). Simulations prove that passive arrays with our analog memory of large current-voltage nonlinearity achieve a high write and recognition accuracy. Thus, our discovery of the unique tunnel memory contributes to an important step toward realizing neuromorphic circuits.

Filamentary and Interface-Type Memristors Based on Tantalum Oxide for Energy-Efficient Neuromorphic Hardware.

To implement artificial neural networks (ANNs) based on memristor devices, it is essential to secure the linearity and symmetry in weight update characteristics of the memristor, and reliability in the cycle-to-cycle and device-to-device variations. This study experimentally demonstrated and compared the filamentary and interface-type resistive switching (RS) behaviors of tantalum oxide (Ta2O5 and TaO2)-based devices grown by atomic layer deposition (ALD) to propose a suitable RS type in terms of reliability and weight update characteristics. Although Ta2O5 is a strong candidate for memristor, the filament-type RS behavior of Ta2O5 does not fit well with ANNs demanding analog memory characteristics. Therefore, this study newly designed an interface-type TaO2 memristor and compared it to a filament type of Ta2O5 memristor to secure the weight update characteristics and reliability. The TaO2-based interface-type memristor exhibited gradual RS characteristics and area dependency in both high- and low-resistance states. In addition, compared to the filamentary memristor, the RS behaviors of the TaO2-based interface-type device exhibited higher suitability for the neuromorphic, symmetric, and linear long-term potentiation (LTP) and long-term depression (LTD). These findings suggest better types of memristors for implementing ionic memristor-based ANNs among the two types of RS mechanisms.

Structural and Electrical Response of Emerging Memories Exposed to Heavy Ion Radiation.

Hafnium oxide- and GeSbTe-based functional layers are promising candidates in material systems for emerging memory technologies. They are also discussed as contenders for radiation-harsh environment applications. Testing the resilience against ion radiation is of high importance to identify materials that are feasible for future applications of emerging memory technologies like oxide-based, ferroelectric, and phase-change random-access memory. Induced changes of the crystalline and microscopic structure have to be considered as they are directly related to the memory states and failure mechanisms of the emerging memory technologies. Therefore, we present heavy ion irradiation-induced effects in emerging memories based on different memory materials, in particular, HfO2-, HfZrO2-, as well as GeSbTe-based thin films. This study reveals that the initial crystallinity, composition, and microstructure of the memory materials have a fundamental influence on their interaction with Au swift heavy ions. With this, we provide a test protocol for irradiation experiments of hafnium oxide- and GeSbTe-based emerging memories, combining structural investigations by X-ray diffraction on a macroscopic, scanning transmission electron microscopy on a microscopic scale, and electrical characterization of real devices. Such fundamental studies can be also of importance for future applications, considering the transition of digital to analog memories with a multitude of resistance states.

An Application Specific Vector Processor for Efficient Massive MIMO Processing

This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22 nm FD-SOI technology running at a clock frequency of 800 MHz. The system achieves a maximum detection throughput of 0.75 Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128\times 8$ </tex-math></inline-formula> massive MIMO system.

Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory.

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a Smart Imaging Sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 µm mixed-signal CMOS process. With a pixel-pitch of 32 µm × 32 µm, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 µm process, achieving a fill factor of 74%. On an array of smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 µs, and has a power consumption of 58 mW.

Entanglement detection with near-zero cost

Recent research on parallel functional programming has culminated in a provably efficient (in work and space) parallel memory manager, which has been incorporated into the MPL (MaPLe) compiler for Parallel ML and shown to deliver practical efficiency and scalability. The memory manager exploits a property of parallel programs called disentanglement, which restricts computations from accessing concurrently allocated objects. Disentanglement is closely related to race-freedom, but subtly differs from it. Unlike race-freedom, however, no known techniques exists for ensuring disentanglement, leaving the task entirely to the programmer. This is a challenging task, because it requires reasoning about low-level memory operations (e.g., allocations and accesses), which is especially difficult in functional languages. In this paper, we present techniques for detecting entanglement dynamically, while the program is running. We first present a dynamic semantics for a functional language with references that checks for entanglement by consulting parallel and sequential dependency relations in the program. Notably, the semantics requires checks for mutable objects only. We prove the soundness of the dynamic semantics and present several techniques for realizing it efficiently, in particular by pruning away a large number of entanglement checks. We also provide bounds on the work and space of our techniques. We show that the entanglement detection techniques are practical by implementing them in the MPL compiler for Parallel ML. Considering a variety of benchmarks, we present an evaluation and measure time and space overheads of less than 5% on average with up to 72 cores. These results show that entanglement detection has negligible cost and can therefore remain deployed with little or no impact on efficiency, scalability, and space.

VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM

VLSI-based programmable devices support improved software-based reconfigurability and hardware performance, which are adopted as developing platforms to implement complex systems, i.e., signal processors, software-defined networks, and image processing applications. Parallel memory allocation (PMA) among various resources plays a crucial role in meeting the high-performance requirements in these applications. The conventional methods were implemented with static random-access memory (SRAM) prototypes, but they failed to meet the maximum data transfer speed. This article focuses on the implementation of error-correctable ternary content-addressable memory (EC-TCAM)-based parallel memory allocation (PMA) systems with error-resilient properties, which can be capable of detecting and correcting errors during the parallel data allocation. Further, the priority circuit is used to generate the different levels of priorities, which helps to transfer the data between master and slave devices and vice-versa. Here, the synchronization issues generated during parallel reading and writing operations are minimized using priority circuit-controlled crossbar switching. The simulation results show the proposed EC-TCAM based PMA resulted in superior performance as compared to the conventional approaches in terms of hardware resource utilization parameters such as slice registers, look up tables (LUTs), LUT-flip-flops (LUT-FFs), delay, and power consumption. Finally, the proposed method utilized 310 slice registers, 235 LUTs, 156 LUT-FFs, 0.793ns of path delay, and 0.065 W of power.

Heterogeneous Integration of Atomically Thin Semiconductors for Non-von Neumann CMOS.

Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high-performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n-type TMDs such as MoS2 and WS2 grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p-type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n-type MoS2 and p-type vanadium doped WSe2 FETs with non-volatile and analog memory storage capabilities to achieve a non-von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n-type and p-type FETs, which is critical for any IC development. Inverters and a simplified 2-input-1-output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non-von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.

Multilevel resistive switching and synaptic behaviors in MnO-based memristor

Exploring new synaptic electronic devices that combine computing and memory is a promising strategy that fundamentally approaches intelligent machines. In this study, the multilevel resistive switching and synaptic behaviors of a MnO-based device is studied. The device is composed of Al/MnO/Ni sandwich structure, has stable resistance switching characteristics, has continuous nonvolatile memory state, can be used as electrically programmable and erasable analog memory. The gradual conductance modulation is realized by changing the compliance current and the maximum scanning voltage. The Al/MnO/Ni devices successfully mimic the basic functions of synapses, including the paired-pulse facilitation, spike-rate-dependent plasticity, excitatory postsynaptic current, short-term plasticity, long-term plasticity, and sike-timing-dependent plasticity.

Linear Frequency Modulation of NbO2-Based Nanoscale Oscillator With Li-Based Electrochemical Random Access Memory for Compact Coupled Oscillatory Neural Network.

Oscillatory neural network (ONN)-based classification of clustered data relies on frequency synchronization to injected signals representing input data, showing a more efficient structure than a conventional deep neural network. A frequency tunable oscillator is a core component of the network, requiring energy-efficient, and area-scalable characteristics for large-scale hardware implementation. From a hardware viewpoint, insulator-metal transition (IMT) device-based oscillators are attractive owing to their simple structure and low power consumption. Furthermore, by introducing non-volatile analog memory, non-volatile frequency programmability can be obtained. However, the required device characteristics of the oscillator for high performance of coupled oscillator have not been identified. In this article, we investigated the effect of device parameters of IMT oscillator with non-volatile analog memory on coupled oscillators network for classification of clustered data. We confirmed that linear conductance response with identical pulses is crucial to accurate training. In addition, considering dispersed clustered inputs, a wide synchronization window achieved by controlling the hold voltage of the IMT shows resilient classification. As an oscillator that satisfies the requirements, we evaluated the NbO2-based IMT oscillator with non-volatile Li-based electrochemical random access memory (Li-ECRAM). Finally, we demonstrated a coupled oscillator network for classifying spoken vowels, achieving an accuracy of 85%, higher than that of a ring oscillator-based system. Our results show that an NbO2-based oscillator with Li-ECRAM has the potential for an area-scalable and energy-efficient network with high performance.

Optimised weight programming for analogue memory-based deep neural networks

Analogue memory-based deep neural networks provide energy-efficiency and per-area throughput gains relative to state-of-the-art digital counterparts such as graphics processing units. Recent advances focus largely on hardware-aware algorithmic training and improvements to circuits, architectures, and memory devices. Optimal translation of software-trained weights into analogue hardware weights—given the plethora of complex memory non-idealities—represents an equally important task. We report a generalised computational framework that automates the crafting of complex weight programming strategies to minimise accuracy degradations during inference, particularly over time. The framework is agnostic to network structure and generalises well across recurrent, convolutional, and transformer neural networks. As a highly flexible numerical heuristic, the approach accommodates arbitrary device-level complexity, making it potentially relevant for a variety of analogue memories. By quantifying the limit of achievable inference accuracy, it also enables analogue memory-based deep neural network accelerators to reach their full inference potential.

Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS2 memristor arrays are reported. The MoS2 memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS2 memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS2 layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

A Linear Time Pattern Based Algorithm for N-Queens Problem

The n-queens problem is the placing of n number of queens on an nxn chessboard so that no two queens attack each other. This problem is important due to various usage fields such as VLSI testing, traffic control job scheduling, data routing, dead-lock or blockage prevention, digital image processing and parallel memory storage schemes mentioned in the literature. Besides, this problem has been used as a benchmark for developing new Artificial Intelligence search techniques. However, it is known that backtracking algorithms, one of the most frequently used algorithms to solve this problem, cannot produce all solutions in large n values due to the exponentially growing time complexity. Therefore, various methods have been proposed for producing one or more solutions, not all solutions for each n value. In this study, a pattern based approach that produces at least one unique solution for all n values (n&amp;gt;3) was detected. By using this pattern, a new algorithm that produces at least one unique solution for even very large n values in linear time was developed. The developed algorithm with О(n) time complexity produces quite faster solution to n-queens problem and even in some values, this algorithm produces (n-1)/2 unique solutions in linear time.

A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/&#x2212;1 and 4.78/&#x2212;3.31 LSB, respectively.

An Integrated Photorefractive Analog Matrix-Vector Multiplier for Machine Learning

AI is fueling explosive growth in compute demand that traditional digital chip architectures cannot keep up with. Analog crossbar arrays enable power efficient synaptic signal processing with linear scaling on neural network size. We present a photonic photorefractive crossbar array for neural network training and inference on local analog memory. We discuss the concept and present results based on the first prototype hardware.

Designing MoS2 channel properties for analog memory in neuromorphic applications

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown.

A parallel model of DenseCNN and ordered-neuron LSTM for generic and species-specific succinylation site prediction.

Lysine succinylation (Ksucc) regulates various metabolic processes, participates in vital life processes, and is involved in the occurrence and development of numerous diseases. Accurate recognition of succinylation sites can reveal underlying functional mechanisms and pathogenesis. However, most remain undetected. Moreover, a deep learning architecture focusing on generic and species-specific predictions is still lacking. Thus, we proposed a deep learning-based framework named Deep-Ksucc, combining a dense convolutional networkand ordered-neuron long short-term memoryin parallel, which took the cascading characteristics of sequence information and physicochemical properties as the input. The results of the generic and species-specific predictions indicated that Deep-Ksucc can identify sequence patterns of different organisms and recognize plenty of succinylation sites. The case study showed that Deep-Ksucc can serve as a reliable tool for biology verification and computer-aided recognition of succinylation sites.

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt; 10\times $ </tex-math></inline-formula> gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

Full-Circuit Implementation of Transformer Network Based on Memristor

As an emerging in-memory element, memristor has been widely used in various neural network circuits to represent the weights and accelerate the calculation. However, the Transformer Network (TN), one of the most important models for machine vision and natural language processing in recent years, has not yet been full-circuit implemented using memristors due to the complex calculation process and data storage. In order to carry out the computation of the TN more efficiently, this work proposes a memristor-based full-circuit implementation of the TN capable of: 1) a memristor crossbar module to preserve the weights of the TN and perform the vector-matrix multiplications; 2) an analog signal memory module to store the analog signal directly in near-memory mode; 3) function circuit modules to achieve five transformations, namely Softmax, Layer Normalization, ReLU, Multiply-add and Residual; 4) a timing signal generation module to schedule operations of the circuit. The proposed TN circuit can complete all calculations directly based on the analog signal without using any analog-digital converter (ADC), digital-analog converter (DAC) and digital memory. In addition, character image recognition experiments are carried out in PSPICE to verify the functional correctness of the designed circuit. The corresponding signal retention rates of the analog memory, the performance of the whole circuit, and the non-idealities of the memristors are also analyzed. The results indicate that the circuit has advantages in terms of area overhead, energy efficiency and anti-noise.