Parallel Decimal Multiplier Research Articles

A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier

Decimal computation is highly demanded in many human-centric applications such as banking, accounting, tax calculation, and currency conversion. Hence the design and implementation of radix-10 arithmetic units attract the attention of many researchers. Among the basic decimal arithmetic operations, multiplication is not only a frequent operation but also has high complexity and considerable power consumption. Therefore, this paper concentrates on this issue and studies a general design methodology that reduces power/energy consumption via localizing switching activity without compromising target performance. This method decomposes a digit multiplier into smaller ones, like Karatsuba’s algorithm, while the multiplicand and the multiplier can be partitioned into different sizes. We take advantage of various size partitions in two types of symmetric and asymmetric, which final designs provide specific characteristics. All designs were implemented using VHDL and synthesized in the Design-Compiler toolbox with TSMC 130 nm Technology file. The results are significant; in respect to the original design, by a random test vector, 25% power reduction is achieved with no effect on latency and a negligible area penalty. Moreover, the experimental results indicate a potential for considerable reduction of power dissipation based on statistical properties of possible input data.

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

A Parallel Decimal Multiplier Based on a novel 4:2 Fully Redundant Decimal Adder

Due to requirements for computational accuracy in the fields of business computing, the decimal arithmetic computing system has gradually become a research hotspot. A parallel decimal multiplication consists of three stages: partial product generation (PPG), partial product reduction (PPR) and the final product generation (FPG). In the PPR stage, a novel 4:2 fully redundant decimal adder based overloaded decimal digit set (ODDS) is proposed in this paper. The 4:2 ODDS adder is formed by the binary 4:2 compressors, a decimal compressor and a converter. Moreover, the signed-digit radix-10 code, the redundant excess-3 code and the ODDS code are used in the PPG stage. In the FPG stage, an ODDS–BCD conversion is adopted to quickly generate BCD-8421 product. The analysis and comparison by using the 45nm technology show that the proposed decimal multiplier based on the 4:2 ODDS adder has less area and better synthesis performance.

Improving the area of fast parallel decimal multipliers

Financial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation.

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature.

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

Decimal $X\times Y$ multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix- $10~X$ multiples. Some works require only $[{ 0, 5 }]\times X$ via recoding digits of $Y$ to one-hot representation of signed digits in $ [-5, 5]$ . This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one xor per bit of $X$ multiples) is required for the recoded digits of $Y$ in $[-5, -1]$ . In this paper, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save 75% of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:1 reduction leads to two TCSD accumulated partial products, which collectively undergo a special early initiated conversion scheme to get at the final binary-coded decimal product. As such, a VLSI implementation of $16\times 16$ -digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs.

A comparative study of energy/power consumption in parallel decimal multipliers

Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today׳s digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of parallel decimal multipliers, considering energy/power consumption, leakage and dynamic power consumption, beside latency and area. This study can provide some guidelines for EDA tools and hardware designers to choose proper multiplier based on given applications and design constraints. All designs in were implemented using VHDL and synthesized in Design-Compiler toolbox with TSMC 45nm technology file.

제한된 범위의 Signed-Digit Number 인코딩을 이용한 병렬 십진 곱셈기 설계

본 논문에서는 제한된 범위의 Signed-Digit number 인코딩과 축약 단계를 이용한 고정소수점 병렬 십진 곱셈기를 제안한다. 제안한 병렬 십진 곱셈기는 승수와 피승수를 제한된 범위의 SD number로 인코딩하여 캐리 전달 지연 없이 빠르게 부분곱을 생성한다. 인코딩에 사용하는 숫자의 범위를 줄임으로써 SD number 다중 피연산자 덧셈의 한번에 연산 가능한 피연산자의 개수가 늘어나게 되고, 이에 따라 부분곱 축약 단계의 연산을 빠르게 수행 할 수 있다. 제안한 병렬 십진 곱셈기의 성능 평가를 위해 Design Compiler에서 SMIC사의 180nm CMOS 공정 라이브러리를 이용하여 합성한 결과 기존의 Signed-Digit number를 이용한 병렬 십진 곱셈기보다 전체 지연시간은 4.3%, 전체 면적은 5.3% 감소함을 확인 하였다. 전체 지연시간 및 면적에서 부분곱 축약 단계가 차지하는 비중이 가장 크므로 부분곱 생성 단계에서 약간의 지연시간 및 면적 증가가 있음에도 불구하고 전체 지연시간과 면적이 감소하는 결과를 얻을 수 있다.

Improving the Energy/Power Consumption of Parallel Decimal Multipliers

Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today’s digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations show 11.5% improvement in terms of total power consumption and 10.13% improvement in terms of energy consumption.

Improving the Energy/Power Consumption of Parallel Decimal Multipliers.

Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today’s digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations show 11.5% improvement in terms of total power consumption and 10.13% improvement in terms of energy consumption.

RADIX-10 PARALLEL DECIMAL MULTIPLIER

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters.

Improved Design of High-Performance Parallel Decimal Multipliers

The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication.

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008decimal64data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.

A fully redundant decimal adder and its application in parallel decimal multipliers

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast computation of the transfer digit and interim sum. In the proposed fully redundant adder (VS semi-redundant ones such as decimal carry-save adders) both operands and sum are redundant decimal numbers with overloaded decimal digit set [0, 15]. This adder is shown to improve upon the latest high performance similar works and outperform all the previous alike adders. However, there is a drawback that the adder logic cannot be efficiently adapted for subtraction. Nevertheless, this adder and its restricted-input varieties are shown to efficiently fit in the design of a parallel decimal multiplier. The two-to-one partial product reduction ratio that is attained via the proposed adder has lead to a VLSI-friendly recursive partial product reduction tree. Two alternative architectures for decimal multipliers are presented; one is slower, but area-improved, and the other one consumes more area, but is delay-improved. However, both are faster in comparison with previously reported parallel decimal multipliers. The area and latency comparisons are based on logical effort analysis under the same assumptions for all the evaluated adders and multipliers. Moreover, performance correctness of all the adders is checked via running exhaustive tests on the corresponding VHDL codes. For more reliable evaluation, we report the result of synthesizing these adders by Synopsys Design Compiler using TSMC 0.13μm standard CMOS process under various time constrains.