Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

Abstract

Decimal $X\times Y$ multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix- $10~X$ multiples. Some works require only $[{ 0, 5 }]\times X$ via recoding digits of $Y$ to one-hot representation of signed digits in $ [-5, 5]$ . This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one xor per bit of $X$ multiples) is required for the recoded digits of $Y$ in $[-5, -1]$ . In this paper, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save 75% of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:1 reduction leads to two TCSD accumulated partial products, which collectively undergo a special early initiated conversion scheme to get at the final binary-coded decimal product. As such, a VLSI implementation of $16\times 16$ -digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs.