A novel design of low power and high speed hybrid multiplier

Abstract

This paper presents the design of a rounded, truncated hybrid multiplier. The maximum absolute error is ensured to be less than one unit of least position. The proposed strategy includes deletion, reduction of partial product bits of multiplier in order to reduce the number of full adders and half adders used during partial product reduction. The high speed computing system requires high-speed and low-power multipliers. This paper proposes a high performance hybrid tree multiplier by using both Wallace and Dadda methods in partial product reduction. The partial products are separated into four groups. Dadda reduction is used in group1 and group4, whereas Wallace tree reduction method is used in the remaining groups. Additionally, the Ling adder is incorporated in the proposed hybrid multiplier in the final stage, to reduce the final carry-propagation delay. The design is implemented, simulated and evaluated using H-SPICE tool with 32nm CMOS predictive technology model(PTM).