A Parallel Decimal Multiplier Based on a novel 4:2 Fully Redundant Decimal Adder

Abstract

Due to requirements for computational accuracy in the fields of business computing, the decimal arithmetic computing system has gradually become a research hotspot. A parallel decimal multiplication consists of three stages: partial product generation (PPG), partial product reduction (PPR) and the final product generation (FPG). In the PPR stage, a novel 4:2 fully redundant decimal adder based overloaded decimal digit set (ODDS) is proposed in this paper. The 4:2 ODDS adder is formed by the binary 4:2 compressors, a decimal compressor and a converter. Moreover, the signed-digit radix-10 code, the redundant excess-3 code and the ODDS code are used in the PPG stage. In the FPG stage, an ODDS–BCD conversion is adopted to quickly generate BCD-8421 product. The analysis and comparison by using the 45nm technology show that the proposed decimal multiplier based on the 4:2 ODDS adder has less area and better synthesis performance.