Improved designs of digit-by-digit decimal multiplier

Abstract

Decimal multiplication is a ubiquitous operation which is inherently complex in terms of partial product generation and accumulation. In this paper, the authors propose a generalized design approach and architectural framework for ‘digit-by-digit’ multiplication. Decimal partial products are generated in parallel using fast and area efficient BCD digit multipliers and their reduction is achieved using hybrid multi-operand binary-to-decimal converters. In contrast to most of the previous implementations, which propose changes either in partial product generation or reduction, this work proposes modifications at both partial product generation and reduction stages resulting in an improved performance. A comprehensive analysis of synthesis results (consistent with IEEE-compliant 16-digit decimal multiplier architecture) indicates an improvement in delay of 8–29% and a reduced area-delay product of 4–38% compared to similar work published previously.