P-type Si Wafers Research Articles

Measurement of the Seebeck coefficient under high pressure by dual heating.

This study presents a new method for measuring the Seebeck coefficient under high pressure in a multi-anvil apparatus. The application of a dual-heating system enables precise control of the temperature difference between both ends of the sample in a high-pressure environment. Two pairs of W-Re thermocouples were employed at both ends of the sample to monitor and control the temperature difference, and independent probes were arranged to monitor the electromotive force (emf) produced by temperature oscillation at a given target temperature. The temperature difference was controlled within 1 K during the resistivity measurements to eliminate the influence of the emf owing to a sample temperature gradient. The Seebeck measurement was successfully measured from room temperature to 1400 K and was obtained by averaging the two measured values with opposite thermal gradient directions (∼20 K). Thermoelectric properties were measured on disk-shaped p-type Si wafers with two different carrier concentrations as a reference for high Seebeck coefficients. This method is effective to determine the thermoelectric power of materials under pressure.

Properties of P-type porous silicon bombarded by neutrons

Nano-porous silicon has been prepared by electrochemical etching a cell of p-type Si wafer for different etching times (20, 35, and 45 min). The samples have been exposed to an average neutron flux of 2 × 108 neutrons/cm2. Transmission electron microscope (TEM) images show an increase of porous width with increasing etching time, which gets larger in diameter after irradiation. Besides, the Raman scattering measurements exhibit a redshift and a considerable stronger asymmetry after irradiation. Photoluminescence (PL) spectra reveal the formation of a PSi layer with stronger PL intensity and redshift region in comparison to the PSi samples before radiation. Therefore, the impact of neutron radiation on the PSi characteristics has a significant fingerprint in the formation of a homogeneous porous layer.

In-Situ Deposition of Graphene Oxide Catalyst for Efficient Photoelectrochemical Hydrogen Evolution Reaction Using Atmospheric Plasma.

The vacuum deposition method requires high energy and temperature. Hydrophobic reduced graphene oxide (rGO) can be obtained by plasma-enhanced chemical vapor deposition under atmospheric pressure, which shows the hydrophobic surface property. Further, to compare the effect of hydrophobic and the hydrophilic nature of catalysts in the photoelectrochemical cell (PEC), the prepared rGO was additionally treated with plasma that attaches oxygen functional groups effectively to obtain hydrophilic graphene oxide (GO). The hydrogen evolution reaction (HER) electrocatalytic activity of the hydrophobic rGO and hydrophilic GO deposited on the p-type Si wafer was analyzed. Herein, we have proposed a facile way to directly deposit the surface property engineered GO.

Optical Modulation in Hybrid Waveguide Based on Si-ITO Heterojunction

An Optical modulator based on a hybrid optical waveguide made up of Silicon and Indium Tin Oxide (ITO) is proposed. The hybrid waveguide is created by the coupling of a leaky optical mode guided in silicon with ITO. The optical modulation is realized with the heterojunction between p-type silicon and n-type ITO. The presence of ITO causes electrical tuning in permittivity and in imaginary-part of the refractive index which provide a way to modulate the intensity of the guide optical mode. The device with Si-ITO heterojunction is fabricated to show intensity modulation at 1.55 μm wavelength. To achieve an efficient optical modulation the carrier concentration of ITO is optimized by depositing ITO on p-type Si wafer at different oxygen partial pressures using Ion assisted electro-beam deposition. The fabricated device exhibiting an extinction ratio of 7 dB for 1.7 mm long device at low voltage of −5 volts.

Fabrication and studies on Si/InP core-shell nanowire based solar cell using etched Si nanowire arrays

We report Si/InP core-shell nanowire radial heterojunction array based solar cell. Silicon nanowire (SiNW) arrays were fabricated by room temperature metal assisted chemical etching method on a p-type Si (100) wafer using silver nanoparticles whereas n-InP layer, as a shell, was deposited onto the SiNW arrays by atmospheric pressure metal organic chemical vapor deposition to obtain core-shell radial heterojunctions. A 100 nm transparent conductive oxide layer was deposited onto top of n-InP layer by sputtering. Transmission electron microscope images confirm the formation of Si/InP core-shell radial nanowire heterostructure. From the studies of reflectance spectroscopy, higher absorption of visible photons has been found. Current-voltage measurements on the radial core-shell nanowire heterojunction based solar cell have been taken under dark and an AM 1.5 solar radiation at room temperature. The device is found to provide a conversion efficiency of 4.39% with an open circuit voltage of 0.56 V and a short circuit current density 14.26 mA/cm2 under AM 1.5 solar radiation. The core-shell radial heterojunction solar cell on nanowire arrays shows great improvement of the performance in comparison with conventional nanowire based solar cells. Our study provides new insights into the Si/InP core-shell nanowire based heterojunction which can have potential applications in fabricating nanoscale optoelectronic devices on Si platform.

Electrochemical Production of Si without Generation of CO2 Based on the Use of a Dimensionally Stable Anode in Molten CaCl2.

The current Si production process is based on the high-temperature (1700 °C) reduction of SiO2 with carbon that produces large amounts of CO2 . We report an alternative low-temperature (850 °C) process based on the reduction of SiO2 in molten CaCl2 that does not produce CO2 . It utilizes an anode material (Ti4 O7 ) capable of sustained oxygen evolution. Two types of this anode material, dense Ti4 O7 and porous Ti4 O7 , were tested. The dense anode showed a better performance. The anode stability is attributed to the formation of a protective TiO2 layer on its surface. In situ periodic current reversal and ex situ H2 reduction could be used for extending the lifetime of the anodes. The findings show that this material can be applied as a recyclable anode in molten CaCl2 . Si wires, films, and particles were deposited with this anode under different cathodic current densities. The prepared Si film exhibited ≈30-40 % of the photocurrent response of a commercial p-type Si wafer, indicating potential use in photovoltaic cells.

Humidity and Temperature Annealing Effect on Light Emission Characteristics of SSI-LEDs

The solid-state incandescent light emitting device (SSI-LED) can emit the broadband white light similar to that of the sunlight in the visible wavelength range [1-4]. The light emitting principle is the thermal excitation of nano-resistors formed from the dielectric breakdown of a MOS capacitor [5]. The intensity of the emitted light is proportional to the intensity of the current passing through nano-resistors [6]. The SSI-LED has a long lifetime of more than 20,000 hours [7]. There are many potential applications of this kind of device, such as lighting and on-chip optical interconnect. In this paper, authors investigated the influence of the humidity and temperature exposure on the light emission characteristics of the SSI-LED. The SSI-LED was made from the dielectric breakdown of a MOS capacitor that contained a Zr-doped HfO2 (ZrHfO) gate dielectric on a p-type Si wafer with an ITO gate electrode. The fabrication process is described in refs. 3 and 5. The top ITO gate electrode has a diameter of 200 µm, 300 µm, or 400 µm. Before and after the exposure of the SSI-LED to the 80% humidity at 80℃ for 1 hour (Association Environmental System BHD-403 7316), the emission spectra were measured at the gate voltage (Vg ) of -30 V using a StellawNet spectra detector with the SpetraWiz Shortcut program. Figure 1 shows the spectra of a 200 µm sized device before and after the annealing. The spectrum shifted toward the long wavelength direct after the annealing, i.e., the peak moved from 601 nm to 641 nm. The same phenomenon has been observed on the 300 µm and 400 µm diameter devices. If the temperature can be estimated from the following Wien’s equation [8], the temperature was lowered by the annealing step, i.e., 4,521K vs. 4,822K. T λpeak = 2.898 x 10-3 [1] where T is the temperature in Kelvin and λpeak is the peak wavelength in m. If the color correlated temperature (CCT) is estimated from the SpetraWiz Shortcut program, the number was also lowered after the annealing, i.e., 4,109K vs. 3,801K. Also, the CIE chart location of the device was moved toward the ward light region, i.e., (CIEx, CIEy) (0.384, 0.370) vs. (0.378,0.380). Figure 2 shows curves of the full width at the half maximum (FWHM) of the emission spectrum vs. the diameter of the device before and after the humidity and temperature annealing. The FWHM was increased after the humidity and temperature exposure. It was reported that the diffusion of H2O through the nano-resistor structure can cause the formation of charge transfer complexes [9], which lowers the resistance and changed the emission spectrum. A detailed discussion of the cause will be presented. Lingguang Liu acknowledge the financial support of National Natural Science Foundation of China (Grant Number: 61771382) and the Shaanxi International Science and Technology Cooperation and Exchange Program (2018KW-034). J. Yan, Y. Kuo, and J. Lu, ECS Solid State Lett., 10, H199-H202 (2007)C. Hobbs, et al., IEDM, 30.1.1 - 30.1.4 (2001).Y. Kuo and C.-H. Lin, Appl. Phys. Lett., 102, 031117 (2013)Y. Kuo, IEEE Trans. Elec. Dev., 62(11), 3536-3540 (2015).C.-H. Lin and Y. Kuo, ECS JSS, 3(10), Q182-Q189 (2014).L. L. Liu, X. N Zhang, B.J. Yu, Y. Y. Lin and H. Zhang, Mat. Sci. Semi. Proc., 93, 226-230 (2019).S. Zhang, Y. Kuo, ECS. Trans., 77(2), 79-83(2017)Y. Kuo, and C- H Lin, ECS Solid State Lett., 2(8) Q59-Q61 (2013). Figure 1

Electrical Properties of Monocrystalline Thin Film Si for Solar Cells Fabricated By Rapid Vapor Deposition with Nano-Surface Controlling Double Layer Porous Si in H2

Introduction To reduce the Si thickness with maintaining the high quality is a promising approach to reduce the cost of monocrystalline Si solar cell. A major method to fabricate monocrystalline thin Si is epitaxy by Chemical Vapor Deposition (CVD) and Layer Transfer Process (LTP) as shown in Fig. 1. A seed layer and a sacrificial layer such as double layer porous Si (DLPS) which consist of a Low Porous Layer (LPL) and a High Porous Layer (HPL) are fabricated on the surface of a monocrystalline Si wafer, and then Si is epitaxially deposited on the seed layer. This wafer can then be reused in LTP, thus further reducing the material cost of these Si cells. There remain two challenging issues: (ⅰ) crystal defect introduced during epitaxy caused by the roughness of the seed layer1) and (ⅱ) low deposition rate and yield of epitaxy by CVD. To solve problem (ⅰ), we proposed a Zone Heating Recrystallization (ZHR) method2) to smoothen the DLPS surface as shown in Fig.2. The structure of the DLPS surface can be modified by using an upper lamp heater to scan the surface in one direction and a bottom heater to pre-heat Si substrate. To solve problem (ⅱ), we proposed a Rapid Vapor Deposition (RVD) method3) as shown in Fig.3. By depositing Si under a high vapor pressure by heating the source Si to over 2000℃, the deposition rate of over 10 μm/min with a higher yield is achieved. By applying both the ZHR and RVD methods, we successfully reduced the roughness of a DLPS surface and obtained monocrystalline Si with Si wafer level. The critical effect of lowering the roughness of a DLPS surface to Rms < 0.3 nm was confirmed1)4). In this work, to fabricate high quality solar cells, we investigated the key factors in improving the roughness of a DLPS surface and evaluated the semiconductor properties of monocrystalline thin film Si. Experiment DLPS was prepared by 2-step anodization of p-type monocrystalline Si (100) wafers (≦0.005 Ω・cm) with 2 mA/cm2 and 415 s for LPL and 200 mA/cm2 and 5 s for HPL, respectively. The prepared DLPS were thermally treated by ZHR with adjusting the heat levels of both the upper and bottom heater and the scan rate of the upper heater under H2(0～5%)/N2 atmosphere to investigate the effect of surface oxidation. RVD were carried out with using p-type monocrystalline Si (100) (1-10 Ω・cm) wafers as the source. The thickness of Si was required to be >40 μm to obtain the sufficient light absorbance, but in our RVD apparatus, only <10 µm-thick Si can be fabricated in one deposition due to the structure of the source boats, so Si was epitaxially deposited on DLPS by RVD in 5 time depositions and the film (48 μm-thick) (Sample-1) was obtained. To increase the deposition rate, the tungsten boat to put Si was modified and the film with 35 μm-thick was obtained in one time deposition (Sample-2). The roughness of the DLPS surface were analyzed using atomic force microscopy. To measure the mobility and the carrier concentration, Si was epitaxially deposited directly on non-doped Si (100) (≧1000 Ω・cm) wafer and the hall effect measurement was carried out. The lifetime of obtained Si films were measured after passivated with Al2O3 film on both sides by atomic layer deposition. Results and discussion The minimum roughness of DLPS surface and the heating amount which minimize the roughness of DLPS surface was decreased by changing the atmosphere from N2 to H2/N2. It is supposed that the structural change occurs easier by inhibiting the effect of oxidation, possibly due to the presence of H2. The life time of Sample-2 was much higher than that of Sample-1. In the multiple RVD process, a native oxide film seemed to be formed on the surface of a Si film during re-setting sources in air atmosphere. Thus, a thin Si with almost wafer-level quality was obtained by increase the thickness by RVD in one deposition. Conclusion The importance to inhibit the effect of oxidation during ZHR was clarified. Nearly wafer-level, 35 µm-thick Si was obtained by RVD in one time deposition by increasing deposition rate. Acknowledgements The part of this research was supported by KAKENHI (KIBAN A) and Center for Low Carbon Society Strategy (LCS), JST. 1)K.Hasegawa,C.Takazawa,M.Fujita,S.Noda and M.Ihara,CrystEngComm,20(13),1774-1778(2018). 2)A.Lukianov,K.Murakami,C.Takazawa and M.Ihara,Appl.Phys.Lett.,108(213904),1-4(2016). 3)Y.Yamasaki,K.Hasegawa,T.Osawa and S.Noda,CrystEngComm,18,3404-3410(2016). 4)C.Takazawa,M.Fujita,K.Hasegawa,A.Lukianov,X.Zhang,S.Noda and M.Ihara,ECS Transaction,75(31),11-23(2016). Figure 1

Radiation hardness investigation of heterojunction solar cell structures with TCO antireflection films

Phosphorus doped silicon carbide film as emitter in heterojunction structure was deposited on p-type Si(100) wafers at various deposition conditions by means of PECVD technology using silane (SiH4), methane (CH4), hydrogen (H2) and phosphine (PH3, 2 vol.% in H2) gas as precursors. ITO or IZO film was RF magnetron sputtered on top of the different P doped a-SiC:H(n) film. Irradiation of structures with Xe ions to total fluency 5×1011 cm−2 was performed at room temperature. Influence of phosphorus concentration and type of transparent conducting oxide was investigated. A deeper insight on the impact of irradiation on the electrophysical properties of sample was obtained by the analysis of complex impedance spectra.

Prediction of amorphous phase formation by thermodynamic and kinetic analysis, a Fe-based thin film metallic glass deposited by direct current magnetron sputtering

In this paper, the Miedema’s model and atomic size mismatch (δ factor) were expanded for prediction (Thermodynamic and kinetic analysis) of amorphous structure of an Fe-based thin film system and followed by experimental verification. The Fe44Cr15Mo14Co7C10B5Si5 thin film metallic glass (TFMG) on P-type Si (100) wafer substrate was deposited by a direct current (DC) magnetron sputtering process with an alloy target derived via spark plasma sintering. In addition, phase and microstructural evolutions of TFMG were studied through x-ray Diffraction (XRD), Grazing Incidence x-ray Diffraction (GIXRD), Atomic Force Microscopy (AFM), Field Emission Scanning Electron Microscopy (FESEM) and Transmission Electron Microscopy equipped with Selected Area Electron Diffraction (TEM-SAED) analysis. The enthalpy, Gibbs free energy changes and the δ factor of the alloy thin film were calculated to be −429.73 kJ.mole−1, −433.81 kJ.mole−1 and 16.2, respectively. It can be found that through the Extended Miedema’s model and the δ factor, the amorphous structure for the above TFMG could be achieved. Results of XRD and TEM-SAED analysis showed that the TFMG with an amorphous structure was formed. Smooth and uniform surface with low surface roughness of 1.74 nm was detected by FE-SEM and AFM analysis, respectively.

Effect of In composition on electrical performance of AlInGaN/GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si

Al x In y Ga ( 1 − x − y ) N / GaN heterostructures were grown on 4-in. p-type Si wafers to investigate the effect of In composition in the quaternary nitride layer on the electrical performance of Al2O3/AlInGaN/GaN-based normally-ON metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). From the comparative study of the electrical measurements, it was observed that the transport properties of the devices were relatively poor in the presence of higher In composition in the quaternary-N layer. The deterioration of the electrical characteristics of MIS-HEMTs originated from the formation of deep pits on the AlInGaN epilayer surface caused by the segregation of In atoms during epitaxial growth. However, the formation of such pits was reduced for the quaternary epilayer with lower In content and exhibited better transport performance. A maximum current density (Id,max) of 780 mA/mm with a specific ON-resistance of 0.71mΩcm2 was observed for the device fabricated on the wafer with an In composition of 9% in the AlInGaN epilayer. We have achieved a high breakdown voltage of 793 V with a device with the gate-to-drain distance (Lgd) of 20μm under the off-state condition.

Gate Screening on Remote Phonon Scattering for Pentacene Organic TFTs: Holes Versus Electrons

Bottom-gated pentacene organic thin-film transistors (OTFTs) were fabricated on p-type and n-type Si wafers with different resistivities, with NdTaON as a high- ${k}$ gate dielectric. Although the pentacene grain size and dielectric surface roughness were nearly the same for all the samples, the carrier mobility improved with decreasing resistivity for both types of OTFTs (p-gate and n-gate), indicating that similar to the electron concentration, the hole concentration in the gate electrode can also affect the carrier mobility. This is attributed to the remote phonon scattering of the high- ${k}$ gate dielectric on the channel carriers, which can be screened by the holes in the gate electrode. The p-gate and n-gate samples with the lowest gate–electrode resistivity of $0.005~\Omega \cdot $ cm achieve the highest mobility of 1.15 and 1.37 cm $^{{2}}/\text{V}\cdot \text{s}$ , respectively. Moreover, for the same gate-doping concentration, the p-gate sample shows lower mobility than the n-gate sample. This is likely because under a negative gate voltage ( ${V}_{g}$ ), the p-gate is depleted to make the actual ${V}_{g}$ smaller than the applied ${V}_{g}$ , thus resulting in a lower extracted carrier mobility. In addition, such a depletion effect leads to a lower hole concentration near the gate–electrode/gate–dielectric interface, thus weakening the gate screening effect on the remote phonon scattering.

Enhanced Operation Characteristics for Charge Trapping Memory with Al2O3/HfO2/Al2O3 High-κ Dielectrics and Sige Substrate

Recent technology advances have moved nonvolatile memory (NVM) to the forefront as key enablers of computing-in-memory for AI chips and nonvolatile logics for IoT devices. Among the family of NVMs, charge trapping memory (CTM) devices has been widely used to realize low power consumption and high speed. In conventional SONOS-type CTM, it becomes hard to improve the program and erase (P/E) speed by optimizing tunneling oxide thickness while still maintaining the retention properties [1]. To confront the challenges faced by SONOS memory, various high-κ dielectrics (Ta2O5, ZrO2, Y2O3, HfO2, etc.) with reduced equivalent oxide thickness (EOT) and improved charge-trapping density are proposed to achieve better memory performance [2-3]. Apart from the adoption of high-κ dielectrics for CTM, the adoption of channel material can also improve memory performance. Recently, some efforts on the utilization of SiGe channel with high electron/hole injection rate have been reported to improve P/E efficiency [4-5]. Electron/hole injection increased because SiGe has a smaller bandgap than silicon. As the electron/hole injection located at tunneling oxide/SiGe channel increases, the number of electrons tunneling through the tunneling oxide is increased and the P/E speed is improved. In this paper, we proposed a novel memory device with high-κ Al2O3/HfO2/Al2O3 nanolaminate, SiGe channel and high work function tungsten metal gate. Finally, a novel charge trapping memory with the structure of [W/TiN]/Al2O3/HfO2/Al2O3/SiGe (named as MAHASG in short) is obtained. MAHASG memory devices with SiGe buried channel, as shown in Fig. 1, were fabricated on p-type Si wafer. Prior to SiGe epitaxial growth, the surface oxide was removed by using a dilute HF 1% solution. Then a 20 nm-thick SiGe epi-layer with 30% Ge content was deposited using reduced pressure chemical vapor deposition (RPCVD). After SiGe epitaxial growth, a 3 nm Al2O3 tunneling layer was deposited by atomic layer deposition (ALD) at a substrate temperature of 300℃. Subsequently, the 7 nm HfO2 film was grown by ALD as the charge trapping layer. Then, another 6-nm thick Al2O3 layer was deposited by ALD in situ as the blocking layer. After that high-κ dielectrics deposition, a post deposition anneal was performed for 15 s at the temperature of 450 °C in N2 atmosphere to improve the material quality of the high-κ dielectrics. Afterwards, TiN/W was deposited as the control gate by ALD and patterned by dry etch, followed by sputtering aluminum as the backside contact. Finally, a metallization process by using forming gas (5% H2, 95% N2) was applied for 30 min and at 400℃. Control samples without HfO2 layer were also fabricated using identical procedure. The resulting structure is shown in Fig 1. It should be noted that the whole process is simple and fully compatible with conventional CMOS technology. The memory characteristics for the MAHASG memory devices were investigated by a Keithley 4200 semiconductor characterization system. In order to study the charge trapping characteristics, bi-directional capacitance-voltage (C-V) curves were obtained by applying different sweeping gate voltages ranging from ±3 V to ±10 V at a frequency of 800 KHz, as shown in Fig. 2. A counterclockwise hysteresis was obtained during voltage sweep from inversion region to accumulation region and then back to inversion region. The memory window is defined as the flat-band voltage shift (ΔVFB) between the forward and backward sweep curves. There is no obvious memory window in the voltage sweep of ±3 V, indicating that charge trapping and de-trapping hardly take place in this voltage sweep range. When the voltage sweep range increases to ±6 V, the memory window is obvious. In a voltage sweep range of ±10 V, a large memory window of about 4 V can be obtained, as indicated in Fig 3. The energy band diagram of the MAHASG memory device is shown in Fig 4. The barrier height for electron injection from the SiGe channel to the HfO2 layer is about 2.74 eV, which is slightly smaller than that of the normal Si-SiO2 system (3.25 eV). This means that a higher charge tunneling probability and program efficiency occurred in this memory structure. In conclusion, this study provides a promising route of future nano-scaled flash memory operation, utilizing high-mobility channel and high-κ materials.

Design Analysis of Heterojunction Solar Cells with Aligned AZO Nanorods Embedded in p-type Si wafer

Higher price-per-watt of silicon (Si) solar cells is still the main bottleneck in their widespread use for power generation due to their expensive manufacturing process. The n-type zinc oxide (n-ZnO) and p-type Si (p-Si) based single heterojunction solar cell is one of the several methods being tried to replace conventional Si single homojunction solar cell technology. In this work, we have explored the possibility of producing photovoltaic materials by employing RF sputtering and hydrothermal technologies. Conductivity of ZnO nanorods has been increased by aluminium (Al) doping. The advantages of using Al doped ZnO (AZO) nanorods (NRs) have been investigated. The integrated reflectance (IR) has been found to be only ~2.86%. Hence, the short circuit current density (Jsc) has been increased by minimizing the reflection loss of solar cells. AZO NR array have been developed over several large area (3″ × 3″) textured p-Si wafers to confirm the repeatability. The maximum efficiency of AZO NRs/Si solar cell of 0.8 cm2 area has been found to be 6.25% for textured p-type Si wafer which is much higher than reported hitherto for this type of solar cell. A simple, low temperature, low cost procedure is thus being proposed, which has the potential of attaining lower cost of production of heterojunction silicon solar cells.

Synaptic device using a floating fin-body MOSFET with memory functionality for neural network

We fabricate a floating fin-body MOSFET with charge trap layer on p-type (1 0 0) Si wafer and investigate the characteristics of the fabricated device as a synaptic device. To implement the long-term potentiation (LTP) and long-term depression (LTD), the change in conductance of the proposed device is investigated by adjusting the amount of charge in charge trap layer. A pair of synaptic device with these LTP and LTD is suggested to express the synaptic weight update in a multi-layer neural network. In addition, we show suitable weight-updating method using the proposed devices for implementing multi-layer neural networks. A 3-layer perceptron network consisted of 784 input, 200 hidden, and 10 output neurons was simulated using the conductance response of the proposed devices. In pattern recognition for 28 × 28 MNIST handwritten patterns, high learning performance with a classification accuracy of 95.74% is obtained when the unidirectional weight update method (B) is used.

Low Energy Effect of Electron Beam Irradiation on Si Solar Cells.

We investigated the change in the cell efficiency resulting from electron beam accelerated irradiation to understand the possibility of using silicon solar cells with nano-surfaces for satellites. The Si solar cells were made of 6″ micro-textured p-type Si wafers. The Si solar cells were fabricated using a standard cell fabrication process, including POCl₃ diffusion, anti-reflection coating layer deposition, and metal contact and co-firing heat treatment. After manufacturing the cell, we irradiated the cell with a low-energy electron beam to determine its effect. We analyzed the changes in the cell resulting from the irradiation with the electron beam by evaluating the photo-reflectance, transmission electron microscopy, electroluminescence and current-voltage curve.

Nanosecond laser ablation of Si(111) under an aqueous medium

Nanosecond laser ablation of p-type Si(111) wafer is presented under an ambient, a water and a glycerin conditions. Effects of pulse energy, number of pulses and type of environment are systematically analyzed with an Optical Profilometer, a Scanning Electron Microscope and an Atomic Force Microscope. Obtained results are compared with Zemax∘-EE simulations. Self-assembly nano-ripple formation has been observed in an ambient condition. However, these ripples and heat affected zone (HAZ) area disappeared in aqueous medium which enhances the quality of ablation. Moreover, no remarkable oxidation was obtained in ablation zone even in an ambient condition based on the SEM-EDX analysis. Ablation profiles and their depths for different environments are compared with false color technique. Although ablation diameters are comparable each other, their depths are small enough in aqueous medium to control depth profile of damaged area. According to our results, best ablation profiles (precise edges without HAZ) are achieved under an aqueous medium especially in glycerin conditions both in low and high pulse energy regime.

Electrical transport phenomena in nanostructured porous-silicon films

The charge transport mechanisms in nanostructured porous silicon (PS) films were studied through current-voltage (I-V) measurements of planar Au/PS/Au structures at 300 K. The films were formed by electrochemical etching of 1-5 Ω-cm p-type Si (100) wafers producing PS layers of 4.48 x 109 Ω-cm. The charge transport is limited both by the space charge limited currents (SCLC) and the carrier trapping-detrapping kinetics in the inherent localized PS energy levels. I-V characteristics evolve according to the trapping-detrapping carrier kinetics in the PS films showing that the electrical current can be controlled by applying external electric fields. An equivalent trap filling limiting voltage (VTFL) was identified that shifts between 1 and 3 volts by the carrier trapping-detrapping kinetics from the PS intrinsic defect states. An energy band diagram for the PS films is schematically depicted including the influence of the intrinsic PS defect states. To give a reasonable explanation of the found behavior the existence of a thin silicon oxide film covering the network-like-silicon-nanocrystallites is required, in agreement with the widely accepted PS structural models.

Optimization of phosphorus dopant profile of industrial p-type mono PERC solar cells

Passivated emitter and rear cells (PERC) on p-type Cz Si wafers are currently being migrated to mainstream production, applying the ongoing improvements in recent years. For PERC solar cells, the emitter recombination loss becomes the main loss of the entire cell. Currently, two-step diffusion consisting of low temperature phosphosilicate glass (PSG) deposition and high-temperature drive-in has been widely applied in production and can reduce saturation current density (J0) of the emitter in the passivated area. However, a low contact resistance under metal area cannot be guaranteed. Meanwhile, the determination of the saturation current density J0 in the passivated area is dependent on the injection density during the measurement, and exact calculation of J0,metal is not as convenient as J0,diffusion, which could lead to a wrong assessment in cell analysis. In this study, a three-step diffusion (low-temperature PSG deposition–high-temperature drive-in–low temperature PSG deposition) with low J0 and low Ag-Si contact resistance is investigated and combined with a selective emitter by an etch-back process. The results are compared with a conventional two-step POCl3 diffusion. The accuracy of J0 measurement and J0,metal test method is also discussed. With these improvements, the champion cell efficiency of our PERC solar cells fabricated on 156 × 156 mm2 wafers using screen printing technology and industrial-type process has reached 22.61% with Voc of 684.4 mV and a fill factor of 81.49%, as confirmed by Fraunhofer ISE CalLab PV cells. By implementing the diffusion process to mass production, the average cell-efficiency gain is approximately 0.2% with a median efficiency of 21.7%.

Enhanced photoelectrochemical performance of black Si electrode by forming a pn junction

A pn junction based on the black Si wafer has been prepared for the photoelectrochemical (PEC) applications by a facile chemical etching method combined with thermal diffusion process. And also in this work, a black Si wafer were fabricated by using a commercial multicrystaline Si (mc-Si) wafer as the raw. It was demonstrated that pn junction was beneficial to enhance the PEC performance of a Si photoanode. The mechanism was further clarified by an electrochemical impedance analysis. The improved PEC activity was attributed to a more efficient charge separation inside the solid electrode. Besides, the p-type Si wafer displayed a characteristic of n-type semiconductor, which was explained through a simple energy band model.