Synaptic device using a floating fin-body MOSFET with memory functionality for neural network

Abstract

We fabricate a floating fin-body MOSFET with charge trap layer on p-type (1 0 0) Si wafer and investigate the characteristics of the fabricated device as a synaptic device. To implement the long-term potentiation (LTP) and long-term depression (LTD), the change in conductance of the proposed device is investigated by adjusting the amount of charge in charge trap layer. A pair of synaptic device with these LTP and LTD is suggested to express the synaptic weight update in a multi-layer neural network. In addition, we show suitable weight-updating method using the proposed devices for implementing multi-layer neural networks. A 3-layer perceptron network consisted of 784 input, 200 hidden, and 10 output neurons was simulated using the conductance response of the proposed devices. In pattern recognition for 28 × 28 MNIST handwritten patterns, high learning performance with a classification accuracy of 95.74% is obtained when the unidirectional weight update method (B) is used.