P-type Devices Research Articles

Comparison of n-type and p-type GaAs oxide growth and its effects on frequency dispersion characteristics

The electrical characteristics of n- and p-type gallium arsenide (GaAs) capacitors show a striking difference in the “accumulation” capacitance frequency dispersion. This difference has been attributed by some to a variation in the oxide growth, possibly due to photoelectrochemical properties of the two substrates. We show that the oxide growth on n- and p-type GaAs substrates is identical when exposed to identical environmental and chemical conditions while still maintaining the diverse electrical characteristics. The difference in electron and hole trap time constants is suggested as the source of the disparity of the frequency dispersion for n-type versus p-type GaAs devices.

Complementary inverter circuits based on p-SnO2 and n-In2O3 thin film transistors

Thin film transistors (TFTs) of indium oxide (In2O3) and tin oxide (SnO2) were fabricated on SiO2 gate dielectric using reactive evaporation process. Structural investigation of the films revealed that In2O3 films were polycrystalline in nature with preferred (222) orientation and SnO2 films exhibited amorphous nature. The x-ray photoelectric spectroscopy measurements suggest that SnO2 films were oxygen rich and presume mixed oxidation states of Sn, namely Sn2+ and Sn4+. While the In2O3 based TFTs possess n-type channel conduction, SnO2 based TFTs exhibited anomalous p-type conductivity. Integration of these n- and p-type devices resulted in complementary inverter with a gain of 11.

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD,</sub> and negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.

A novel 10-nm physical gate length double-gate junction field effect transistor

A novel double-gate (DG) junction field effect transistor (JFET) with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.

Integration of PtSi in p-Type MOSFETs Using a Sacrificial Low-Temperature Germanidation Process

In this letter, an original selective etching method of Pt with respect to PtSi using a sacrificial low-temperature germanidation process is used for the integration of valence band edge contacts in p-type MOSFET devices. After silicidation annealing, the excess of Pt due to incomplete reaction with silicon or standing on insulating layers can be transformed into the PtGe2 phase. The solubility of this phase in a sulfuric peroxide mixture (SPM) without altering PtSi is demonstrated. The suitability and scalability of the proposed integration scheme is shown through the successful integration and characterization of PtSi source/drain contacts in p-type MOSFETs.

A systematic study on MOS type radiation sensors

Radiation sensors based on metal oxide semiconductor (MOS) structure are useful because of their superior sensitivity as well as excellent compatibility with the existing microelectronic technology. In this paper, a systematic study of MOS capacitors built on p- and n-type Si substrates with different SiO 2 thicknesses (10 nm, 50 nm, 100 nm and 240 nm) is presented. MOS device response to gamma radiation up to 256 Gray have been studied from the sensor application point of view. Variation of the radiation induced device response with oxide thickness, substrate type, applied bias and post annealing have been measured and discussed. Radiation induced charge in MOS devices is shown to be a strong function of the oxide thickness as expected. Application of a positive bias to the gate is found to enhance the device sensitivity for both n- and p-type devices. This is explained in terms of the involvement of the interface states in the sensing process. Devices have also been studied after repeated cycles of irradiation and annealing treatment under hydrogen atmosphere. Each cycle consists of gamma irradiation with 60 Gray dose and an anneal at 200 °C for 30 min. The charging–discharging mechanism during these cycles is discussed.

Valence Band Offset Measurements on Thin Silicon-on-Insulator MOSFETs

The effect of quantum confinement in thin silicon-on-insulator double-gate MOSFETs has been directly determined from subthreshold current measurements for the first time. By comparing temperature-dependent subthreshold characteristics of p-type devices with different silicon layer thicknesses, the offset in the valence band edge induced by spatial carrier confinement in these very thin silicon layers was measured electrically. Changes in the band structure are important for future CMOS devices such as FinFETs.

Magnetic Czochralski silicon as detector material

The Czochralski silicon (Cz-Si) has intrinsically high oxygen concentration. Therefore Cz-Si is considered as a promising material for the tracking systems in future very high luminosity colliders. In this contribution a brief overview of the Czochralski crystal growth is given. The fabrication process issues of Cz-Si are discussed and the formation of thermal donors is especially emphasized. N +/p −/p + and p +/n −/n + detectors have been processed on magnetic Czochralski (MCz-Si) wafers. We show measurement data of AC-coupled strip detectors and single pad detectors as well as experimental results of intentional TD doping. Data of spatial homogeneity of electrical properties, full depletion voltage and leakage current, is shown and n and p-type devices are compared. Our results show that it is possible to manufacture high quality n +/p −/p + and p +/n −/n + particle detectors from high-resistivity Cz-Si.

Scaling of Strain-Engineered MOSFETs

The aim of the present work is to study the evolution of Si based heterostructure MOSFETs via the incorporation of new materials, for example strained-Si, and to predict the resultant device performance and scaling trends of strained-Si/SiGe MOSFETs for RF applications. The article describes a comprehensive technology CAD (TCAD) based methodology to design and optimize strained-Si channel of CMOS technology using Sentaurus tools. Sentaurus-PROCESS is used to simulate and optimize a typical 90/45-nm process flow, including channel, halo, source/drain (S/D) profile engineering, oxidation, deposition, etching, and annealing for dopant activation. The structure generated by Sentaurus-PROCESS is then simulated using the device simulator Sentaurus-DEVICE. The simulation results have been benchmarked with reported experimental strained-Si channel MOSFET device results. The calibrated n- and p-type devices are scaled down to a 45 nm gate length to assess the device and circuit behavior.

Charge Trapping and TDDB Characteristics of Ultrathin MOCVD $\hbox{HfO}_{2}$ Gate Dielectric on Nitrided Germanium

In this letter, we investigate the long-term reliability characteristics of ultrathin HfO2 dielectrics on nitrided germanium for the first time. Stress-polarity dependence in charge trapping and time-dependent dielectric-breakdown (TDDB) characteristics has been observed in germanium nand p-type devices. The p-MOS devices exhibit severe charge trapping under stress, while no significant charge trapping and stress-induced leakage current were found in the n-MOS devices. In terms of operation-voltage projection for a ten-year lifetime, Vg=2.8 and -2.1 V is projected for the germanium p- and n-MOS devices, respectively, with an equivalent oxide thickness of 11 Aring. Compared to Si control samples, germanium devices show a comparable projected operation voltage, indicating that the TDDB for high-kappa dielectrics on nitrided germanium is not a concern. The stress-polarity dependence in germanium devices is believed to result from the asymmetrical band structure and the significant difference of the electric field strength across the gate dielectric between the positive and negative stress conditions

Organic field-effect transistors based on heterocyclic co-oligomers containing a pyrazine ring

New oligomers containing a pyrazine unit have been prepared: the bithienyl derivatives afforded p-type FET devices whereas the trifluoromethylphenyl derivatives showed n-type FET behavior.

Numerical simulation of hole transport in silicon nanostructures

In order to study the trade-off between accuracy and computational costs in p-type device simulation, we have simulated hole transport in one-dimensional Si p+pp+ structures within a nonequilibrium Green’s function formalism combining with three different types of methods for band structure calculation; an empirical sp3d5s* tight-binding method, k⋅p two-band approximation, and effective-mass approximation.

Selective epitaxial Si/SiGe growth for VT shift adjustment in high k pMOS devices

Downscaling of classical metal oxide semiconductor (MOS) devices resulted in a need to replace the gate oxide by high k dielectrics to keep the gate leakage under control. However, new device issues such as an uncontrollable shift in the threshold voltage in p-type MOS devices and a reduction in channel mobility were encountered. These issues can be overcome by the implementation of buried strained SiGe channels, grown by selective epitaxial growth, as demonstrated in this paper. The optimized high k gate fabrication scheme starts with the growth of a very thin oxide layer. Therefore, a Si cap layer is required because oxidation of SiGe leads to defects at the gate/channel interface. The Si growth rate is influenced by the underlying SiGe layer, during the deposition of the first atomic layers. Nevertheless, accurate thickness control of the Si cap is possible. The minimal required Si cap thickness and its dependence on Ge content in the underlying SiGe channel, for making high-quality dielectrics and maintaining low capacitive equivalent thickness, is extracted from charge pumping measurements, CV measurements and energy dispersive x-ray spectroscopy measurements. Device results demonstrate the successful implementation of buried SiGe channels in pMOS devices with high k gate dielectrics.

Towards the silicon nanowire-based sensor for intracellular biochemical detection

A microneedle sensor platform with integrated silicon nanowire tip was developed for intracellular biochemical detection. Because of the virtue of miniaturized size and high sensitivity, this sensor has a great potential for studying individual cell or localized bioenvironment by revealing the pH level and/or enzyme activities. The fabrication of the microneedle sensor was primarily based on conventional silicon processing, where a silicon-on-insulator (SOI) wafer with 50 nm thick (1 0 0) p-type Si device layer was used as the substrate. The silicon nanowires of 50 nm height and 50–100 nm width were created by electron beam (E-beam) lithography on the tip of microneedle with good electrical connection to the contact pads for convenient electrical measurement. A three layer structure with base, support cantilever, and needle tip was designed to ensure convenient handling of sensors and minimize the invasive penetration into biological cells. In this paper, we demonstrate a preliminary assessment of this novel intracellular sensor with electrical conductance measurement under different pH levels. It is expected that this sensor with proper chemical modification will enable localized biochemical sensing within biological cells, such as neurotransmitter activities during the synaptic communication between neuron cells.

Interaction of solid organic acids with carbon nanotube field effect transistors

A series of solid organic acids were used to p-dope carbon nanotubes. The extent of doping is shown to be dependent on the pKa value of the acids. Highly fluorinated carboxylic acids and sulfonic acids are very effective in shifting the threshold voltage and making carbon nanotube field effect transistors to be more p-type devices. Weaker acids like phosphonic or hydroxamic acids had less effect. The doping of the devices was accompanied by a reduction of the hysteresis in the transfer characteristics. In-solution doping survives standard fabrication processes and renders p-doped carbon nanotube field effect transistors with good transport characteristics.

A study of envelope functions in FD-SOI devices for non-parabolic bands

In this study we analyzed the envelope functions obtained by solving the effective-mass Schrodinger equation including the non-parabolicity of the valence band in p-type FD-SOI devices. In order to carry out this task, we used two different algorithms to solve the effective-mass Schrodinger equation in barriers, and calculated the envelope functions and eigenenergies yielded by these methods for several states along the subbands. This study enabled us to propose a method for selecting the most appropriate envelope functions for each subband. Finally, we quantified the differences in phonon and interface-roughness scattering rates resulting from using the envelope function proposed rather than that obtained by simpler approaches in barriers.

2,6-Bis[2-(4-pentylphenyl)vinyl]anthracene: A Stable and High Charge Mobility Organic Semiconductor with Densely Packed Crystal Structure

The development of new organic semiconductors with improved electrical performance and enhanced environmental stability is the focus of considerable research activity. This paper presents the design, synthesis, optical and electrochemical characterization, crystal packing, modeling and thin film morphology, and organic thin film field effect transistor (OTFT) device data analysis for a novel 2,6-bis[2-(4-pentylphenyl)vinyl]anthracene (DPPVAnt) organic semiconductor. We observed a hole mobility of up to 1.28 cm2/V.s and on/off current ratios greater than 107 for OTFTs fabricated using DPPVAnt as an active semiconductor layer. The mobility value is comparable to that of the current best p-type semiconductor pentacene-based device performance. In addition, we found a very interesting relationship between the charge mobility and molecule crystal packing in addition to the thin film orientation and morphology of the semiconductor as determined from single-crystal molecule packing study, thin film X-ray diffraction, and AFM measurements. The high performance of the semiconductor ranks among the best performing p-type organic semiconductors reported so far and will be a very good candidate for applications in organic electronic devices.

X-ray diffraction studies of the structure and orientations of thiophene and fluorenone based molecule

The crystal structure of a conjugated molecule containing thiophene and fluorenone residues has been determined from powder X-ray diffraction (XRD). Thin films (< 40 nm thick) of this molecule, grown in high vacuum (10 − 5 Pa) onto oxidized silicon substrates, are oriented along with different crystallographic directions. A comparison of XRD in both Grazing Incidence and Bragg–Brentano geometries allowed to perform a quantitative analysis of the various orientations. This approach is generally applicable in the case of multi-oriented films. The results fully account for the poor performance of this molecule in p-type field effect transistor devices.

Radiation-hard detectors for very high luminosity colliders

Recent results from the CERN RD50 Collaboration for the development of radiation-hard detectors for the LHC upgrade (Super-LHC) and in general for very high luminosity colliders are reported and discussed. Particularly, the attention is focused on Czochralski and Magnetic Czochralski silicon, thin detectors and p-type substrate devices.

Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI

AbstractIn this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.