P-channel Metal Oxide Semiconductor Field Research Articles

Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

Non-volatile tuning of normally-on and off states of deep depletion ZrO2/O-terminated high voltage diamond MOSFET

Based on the stability of the deep depletion regime in diamond and the outstanding properties of this promising material for its use in power devices, p-channel deep depletion metal oxide semiconductor field effect transistors were fabricated on a (001) Ib nitrogen-doped high pressure high temperature diamond substrate. Taking advantage of the new concept of the non-volatile diamond-based photo switch, it is demonstrated that it is possible to tune the normally-on and normally-off states of the transistor by configuring the pn-junction space charge region. The devices under study was designed following an interdigital-like and a circular-like architectures presenting low threshold voltages (between 3 V and −3 V), an on/off ratio of 107 and a critical electric field numerically assessed of 9 MV.cm−1 at room temperature. This new degree of freedom opens the route for diamond based power electronics.

An enhanced high frequency performance SiC MOSFET with self-adjusting P-shield region potential

An enhanced high frequency (HF) performance SiC metal oxide semiconductor field effect transistor (MOSFET) with self-adjusting P-shield region potential (SA-MOS) is proposed and characterized in this paper. The potential of P-shield region (ground or floating potential) can be adjusted by a depletion P-channel metal oxide semiconductor field effect transistor (PMOS) structure integrated in the SA-MOS. During turn-on of SA-MOS, the channel of integrated PMOS is pinched off and the P-shield region can be at a floating potential. Therefore, SA-MOS shows about 21% specific on-resistance (R on,sp) reduction as compared to the conventional trench gate SiC MOSFET with grounded P-shield (GP-MOS) due to the retraction of depletion layer in drift region. During turn-off of SA-MOS, the integrated PMOS is turned on and the P-shield region is grounded to the source contact. Thus, the high on-state oxide electric field and slower switching speed caused by the floating P-shield region could be eliminated by SA-MOS structure. Furthermore, the gate-to-drain charge (Q gd) of SA-MOS is only 217 nC cm−2 owing to smaller overlap area between drift region and trench gate, which is about 40% lower than that of GP-MOS. The HF figures of merit (HF-FOM= R on,sp × Q gd) for SA-MOS can be as low as 50% or more of GP-MOS. Finally, an analytical model is also developed to describe the variation of P-shield potential in SA-MOS. With the overall improved performance, SA-MOS shows a significant advantage in HF field in comparison with the GP-MOS.

Enhanced zirconia oxide dielectric quality of germanium p-channel metal oxide semiconductor field effect transistor by in-situ low temperature treatment in atomic layer deposition process

The gate dielectric quality of germanium (Ge) p-channel metal oxide semiconductor field effect transistor (MOSFET) is enhanced by using an in-situ low temperature treatment in atomic layer deposition (ALD) process in this work. With additional oxygen flow or remote oxygen-based plasma, the dangling bond, oxygen vacancy, and oxide traps in the ALD-formed zirconia oxide gate dielectric can be effectively passivated. Unlike the traditional post deposition annealing process that generally causes an increased equivalent oxide thickness (EOT) significantly, the in-situ low temperature treatment can lower the EOT value, reduce the gate leakage current, and improve the gate dielectric quality at the same time. As a result, the sample with an additional oxygen gas flow can exhibit a lower hysteresis value, better frequency dispersion characteristics, higher on/off current ratio, lower sub-threshold swing value, higher transconductance value, higher field effect mobility value, and better uniformity, simultaneously. This dielectric quality enhancement technique with in-situ low temperature process is promising to overcome the trade-off between EOT and gate leakage for the future Ge MOSFET devices.

Experimental and Simulation Analysis of Thermal Vertical Directional Solidification Grown Ni Doped Gasb

Due to high hole mobility, p-GaSb is an attractive III-V semiconducting material for high performance p-channel metal-oxide semiconductor field effect transistor (p-MOSFET). For that growth of undoped and Ni doped GaSb bulk crystal by thermal vertical directional solidification technique has been reported in this paper. X-ray diffraction (XRD) analysis confirms that the both grown compounds are polycrystalline in nature which have been supported by scanning electron microscope (SEM) image. The carrier charge density and mobility were measured by Hall Effect measurement in the temperature range 78K and 300K. From the sign of Hall co-efficient the both grown materials were confirmed p-type. The Current-Voltage (I-V) characteristic was studied for both the sample i.e. experimentally grown and also simulated using TCAD at 78K and 300K. The temperature dependence of the hole mobility were also investigated by TCAD tool using the models Auger recombination, Shockley-Read-Hall (SRH) and Band-gap narrowing (BGN). Comparison of experimental and simulated temperature dependencies of mobility shows good agreement, while their differences at some points suggests the contribution of compensating impurities.

Experimental and Simulation Analysis of Thermal Vertical Directional Solidification Grown Ni Doped Bulk GASB

Due to high hole mobility, p-GaSb is an attractive III-V semiconducting material for high performance p-channel metal-oxide semiconductor field effect transistor (p-MOSFET). For that growth of undoped and Ni doped GaSb bulk crystal by thermal vertical directional solidification has been reported in this paper. Both structural and electrical characterization was carried out for both the samples. X-ray diffraction (XRD) analysis confirms that the compound grown is polycrystalline in nature which has been supported by scanning electron microscope (SEM) image. The carrier charge density and mobility were measured by Hall Effect measurement in the temperature range 78K and 300K. From the sign of Hall co-efficient the grown material was confirmed p-type. The Current-Voltage (I-V) characteristic was studied for the sample i.e. experimentally grown and also simulated using TCAD at 78K and 300K. The temperature dependence of the hole mobility were also investigated by TCAD tool using the models Auger recombination, Shockley-Read-Hall (SRH) and Band-gap narrowing (BGN). Comparison of experimental and simulated temperature dependencies of mobility shows good agreement, while their difference at some points suggests the contribution of compensating impurities.

Negative bias temperature instability in strained-Si p-MOSFETs

Strained-Si p-channel metal oxide semiconductor field effect transistors (MOSFETs) have become the performance boosters beyond 90 nm technology node. Reliability study of these devices is essential as only a few reports are available on this. In this work, we have explored the degradation mechanisms in these devices due to negative bias temperature instability (NBTI). Device simulation results have been calibrated with reported experimental data and a good agreement is observed. The reliability study of these devices has been performed using the two-stage model for defect creation. Study of the drain current degradation and comparison of threshold voltage shift after stressing between the strained-Si and Si channel p-MOSFETs have been performed. The threshold voltage degradation in strained-Si channel p-MOSFETs is found to be considerably higher than that in the bulk-Si devices due to higher fixed oxide charge and interface trap densities at the strained-Si/SiO2 interface.

Negative bias temperature instability in strained-Si p-MOSFETs

Strained-Si p-channel metal oxide semiconductor field effect transistors (MOSFETs) have become the performance boosters beyond 90 nm technology node. Reliability study of these devices is essential as only a few reports are available on this. In this work, we have explored the degradation mechanisms in these devices due to negative bias temperature instability (NBTI). Device simulation results have been calibrated with reported experimental data and a good agreement is observed. The reliability study of these devices has been performed using the two-stage model for defect creation. Study of the drain current degradation and comparison of threshold voltage shift after stressing between the strained-Si and Si channel p-MOSFETs have been performed. The threshold voltage degradation in strained-Si channel p-MOSFETs is found to be considerably higher than that in the bulk-Si devices due to higher fixed oxide charge and interface trap densities at the strained-Si/SiO2 interface.

Enhancement of mobility in ultra-thin-body GeOI p-channel metal–oxide–semiconductor field effect transistors with Si-passivated back interfaces

Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates with Si-passivated back interfaces have been fabricated by using advanced epitaxial-lift-off (ELO) technology. Performance of UTB GeOI p-MOSFETs with body thickness (Tbody) in the 4–16 nm range has also been characterized. Si-passivated back interfaces have been fabricated and found to be effective in mitigating the unpleasant hole-mobility degradation in the UTB GeOI regime owing to the suppression of the back interface scattering.

Improvement of the short channel effect in PMOSFETs using cold implantation

In this paper, to suppress transient enhanced dopant diffusion and improve short channel effects, cold implantation (cold-IIP) was applied to contact PLUG implantation in P-channel metal oxide semiconductor field effect transistors (PMOSFETs). A shallow dopant profile was formed by the suppression of transient enhanced diffusion (TED) due to the reduction of end-of-range (EOR) defects. Threshold voltage roll-off and off current (Ioff) increment, which are caused by a reduction in the distance between the gate and contact, were improved compared with room temperature implantation (RT-IIP). Additionally, the drain induced barrier lowering was improved, and the on-current improvement was attributed to reducing the contact resistance through the reduction of EOR defects. The contact resistance was reduced by ∼6% of the RT-IIP. In the DRAM device, the standby current at a short propagation delay time (tPD) was reduced effectively due to the decrease in the Ioff and contact resistance for the cold-IIP case.

High performance strained Si0.5Ge0.5 quantum-well p-MOSFETs fabricated using a high-κ/metal-gate last process

A high-κ/metal-gate (HKMG) last process for fabricating strained Si0.5Ge0.5 quantum-well (QW) p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) is presented. Because the HKMG was formed after the ion-implant doping activation process, the thermal budget issue could be mitigated. The transistor features good transfer and output characteristics with Ion/Ioff ratio up to 106 and threshold voltage (VT) down to 0.1V. The effective hole mobility of the SiGe QW transistor reaches 215cm2/Vs for strong inversion conditions, which is 2.74 times the SOI device’s hole mobility.

Threshold voltage shifts and their variability behaviors in p-channel FETs by high voltage on-state and off-state stress

This paper presents threshold voltage shifts (Δ|Vth|) and their variability in p-channel metal–oxide–semiconductor field effect transistors (pMOSFETs) by the high voltage ON- and OFF-state stress. Measurement data show that Δ|Vth| in pFETs by the high voltage ON- and OFF-state stress depends on gate length and gate width. Larger positive Δ|Vth| by the ON-state stress is obtained in shorter gate length and narrower gate width pFETs and the negative Δ|Vth| by the OFF-state stress is observed only in the narrowest pFETs. It is also found that variability of Δ|Vth| by the ON-state stress shows normal distribution and roughly follows the Pelgrom plot, indicating that the total trapped charges by the ON-state stress are randomly placed. These measurement data provide clear device design guidelines for the post-fabrication self-improvement scheme of static random access memory (SRAM) cell stability.

Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors

Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.

60Co-Gamma Ray Induced Total Dose Effects on P-Channel MOSFETs

Total Dose Effect (TDE) on solid state devices is of serious concern as it changes the electrical properties leading to degradation of the devices and failure of the systems associated with them. Ionization caused due to TDE in commercial P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied, where the failure mechanism is found to be mainly a result of the changes in the oxide properties and the surface effects at the channel beneath the gate oxide. The threshold voltage of the MOSFETs was found to shift from −0.69 V to −2.41 V for a total gamma dose of 1 Mrad. The net negative threshold shifts in the irradiated devices reveal the major contribution of oxide trapped charges to device degradation. The radiation induced oxide and interface charge densities were estimated through subthreshold measurements, and the trap densities were found to increase by one order in magnitude after a total gamma dose of 1 Mrad. Other parameters like transconductance, subthreshold swing, and drain saturation current are also investigated as a function of gamma dose.

Abnormal threshold voltage shift under hot carrier stress in Ti1−xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors

This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1−xNx p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S.S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (Vd). However, our experimental data indicate that S.S. has no evident change under CHCS, but threshold voltage (Vth) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such Vth degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different Vth behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1−xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-Nit occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior.

Refined NBTI characterization of arbitrarily stressed PMOS devices at ultra-low and unique temperatures

We reexamine degradation and recovery dynamics in the negative bias temperature instability (NBTI) of p-channel metal oxide semiconductor field effect transistors (PMOSFETs) by making use of the recently developed in situ polyheater technique. The capability of switching the device temperature extremely fast and almost arbitrarily allows for measuring differently stressed devices directly after the termination of stress at a unique and much lower characterization temperature (e.g. −60°C). This procedure (‘degradation quenching’) is a powerful extension of the conventional measure–stress–measure (MSM) technique and provides a cleaner way for comparing threshold voltage shifts and charge pumping (CP) currents of arbitrarily stressed devices. We find that increasing the stress bias predominantly activates a larger number of defects with similar (short) recovery time constants causing steeper threshold voltage recovery transients after the termination of stress. Increasing the stress temperature has a very similar effect on the threshold voltage shift as increasing the stress time. In both cases, defects with larger recovery time constants are activated while the number of defects with short recovery time constants remains essentially the same. A comparison of VTH shift and CP data suggests that the total threshold voltage shift is due to at least two fundamentally different types of defects, one being readily recoverable and uncorrelated to the CP current while the other is ‘quasi-permanent’ and proportional to the CP current. By converting CP currents into corresponding threshold voltage shifts, we find that only about 50% of the ‘quasi-permanent’ VTH damage is due to slowly-recoverable interface states. The remaining fraction is due to another, yet undefined, positively charged defect generated at virtually the same rate.

Insight into the multicomponent nature of negative bias temperature instability

A novel measurement technique is used to extract two physically distinct “permanent” (long lived on our experimental time scale, ≤12 000 s) and one recoverable charge components of the negative bias temperature instability in p-channel metal–oxide–semiconductor field effect transistors under inversion and n-channel devices under accumulation. The results suggest that the permanent components are present in both cases, while there is little, if any, recoverable charge present in the case of the n-channel device. A physical explanation is provided involving the band energy diagram to explain these observations.

Uniaxial stress effect and hole mobility in high-Ge content strained SiGe (110) P-channel metal oxide semiconductor field effect transistors

The hole mobility in a high Ge-content (110) SiGe inversion layer is measured and simulated by a split capacitance–voltage method and a quantized k⇀·p⇀ method, respectively. The calibrated model reproduces our experimental channel mobility measurements for the biaxial compressive strain SiGe on (110) substrate. We also explore the impact of external mechanical uniaxial stress on the SiGe (110) p-channel metal oxide semiconductor field effect transistor (PMOSFET). We obtained the corresponding piezoresistance coefficients of the SiGe (110) PMOSFET with external mechanical uniaxial stress parallel and perpendicular to the channel direction. Our study shows the effectiveness in combining external mechanical uniaxial stress and intrinsic biaxial compressive strain for the SiGe (110) PMOSFET.

A Wide Dynamic Range CMOS Image Sensor Based on a Pseudo 3-Transistor Active Pixel Sensor Using Feedback Structure

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

Highly Sensitive Gate/Body-Tied P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector with an Overlapping Control Gate

In this paper, a highly sensitive gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with an overlapping control gate is proposed. The proposed photodetector has an overlapping control gate that makes it possible to control the sensitivity of the proposed photodetector. This sensitivity controllability extends the dynamic range and provides a high sensitivity in a low-light environment. The body of the proposed gate/body-tied PMOSFET-type photodetector is connected to the floating gate, and the control gate is placed on top of the floating gate. The proposed device was fabricated using a 0.35 µm standard complementary metal oxide semiconductor (CMOS) process. The amplified photocurrent of the proposed device was more than 100 times larger than that of a conventional n+/p-sub photodiode with the same area. The area of the proposed photodetector is 3.8×4.4 µm2, which is 24% smaller than that of a conventional gate/body-tied PMOSFET-type photodetector with a transfer gate. Therefore, the proposed photodetector can be suitable for high-sensitivity active pixel sensors (APSs) because of its much higher responsivity than that of a conventional n+/p-sub photodiode.