P-channel Metal Oxide Semiconductor Field-effect Research Articles

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Experimental and Simulation Analysis of Thermal Vertical Directional Solidification Grown Ni Doped Gasb

Due to high hole mobility, p-GaSb is an attractive III-V semiconducting material for high performance p-channel metal-oxide semiconductor field effect transistor (p-MOSFET). For that growth of undoped and Ni doped GaSb bulk crystal by thermal vertical directional solidification technique has been reported in this paper. X-ray diffraction (XRD) analysis confirms that the both grown compounds are polycrystalline in nature which have been supported by scanning electron microscope (SEM) image. The carrier charge density and mobility were measured by Hall Effect measurement in the temperature range 78K and 300K. From the sign of Hall co-efficient the both grown materials were confirmed p-type. The Current-Voltage (I-V) characteristic was studied for both the sample i.e. experimentally grown and also simulated using TCAD at 78K and 300K. The temperature dependence of the hole mobility were also investigated by TCAD tool using the models Auger recombination, Shockley-Read-Hall (SRH) and Band-gap narrowing (BGN). Comparison of experimental and simulated temperature dependencies of mobility shows good agreement, while their differences at some points suggests the contribution of compensating impurities.

Experimental and Simulation Analysis of Thermal Vertical Directional Solidification Grown Ni Doped Bulk GASB

Due to high hole mobility, p-GaSb is an attractive III-V semiconducting material for high performance p-channel metal-oxide semiconductor field effect transistor (p-MOSFET). For that growth of undoped and Ni doped GaSb bulk crystal by thermal vertical directional solidification has been reported in this paper. Both structural and electrical characterization was carried out for both the samples. X-ray diffraction (XRD) analysis confirms that the compound grown is polycrystalline in nature which has been supported by scanning electron microscope (SEM) image. The carrier charge density and mobility were measured by Hall Effect measurement in the temperature range 78K and 300K. From the sign of Hall co-efficient the grown material was confirmed p-type. The Current-Voltage (I-V) characteristic was studied for the sample i.e. experimentally grown and also simulated using TCAD at 78K and 300K. The temperature dependence of the hole mobility were also investigated by TCAD tool using the models Auger recombination, Shockley-Read-Hall (SRH) and Band-gap narrowing (BGN). Comparison of experimental and simulated temperature dependencies of mobility shows good agreement, while their difference at some points suggests the contribution of compensating impurities.

Enhancement of mobility in ultra-thin-body GeOI p-channel metal–oxide–semiconductor field effect transistors with Si-passivated back interfaces

Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates with Si-passivated back interfaces have been fabricated by using advanced epitaxial-lift-off (ELO) technology. Performance of UTB GeOI p-MOSFETs with body thickness (Tbody) in the 4–16 nm range has also been characterized. Si-passivated back interfaces have been fabricated and found to be effective in mitigating the unpleasant hole-mobility degradation in the UTB GeOI regime owing to the suppression of the back interface scattering.

Threshold voltage shifts and their variability behaviors in p-channel FETs by high voltage on-state and off-state stress

This paper presents threshold voltage shifts (Δ|Vth|) and their variability in p-channel metal–oxide–semiconductor field effect transistors (pMOSFETs) by the high voltage ON- and OFF-state stress. Measurement data show that Δ|Vth| in pFETs by the high voltage ON- and OFF-state stress depends on gate length and gate width. Larger positive Δ|Vth| by the ON-state stress is obtained in shorter gate length and narrower gate width pFETs and the negative Δ|Vth| by the OFF-state stress is observed only in the narrowest pFETs. It is also found that variability of Δ|Vth| by the ON-state stress shows normal distribution and roughly follows the Pelgrom plot, indicating that the total trapped charges by the ON-state stress are randomly placed. These measurement data provide clear device design guidelines for the post-fabrication self-improvement scheme of static random access memory (SRAM) cell stability.

New Simulation Method to Characterize the Recoverable Component of Dynamic Negative-Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

We introduce a new simulation technique to investigate the recovery characteristics of dynamic negative-bias temperature instability (NBTI) in conventional silicon dioxide (SiO2) dielectric p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs) based on the hydrogen diffusion and hole-trapping mechanisms. In this work, a sequence of train pulses on the gate terminal were applied to simulated p-MOSFETs in single and multiple runs, thus emulating repetitive cycles of stress and recovery. The effects of varying the applied stress voltages, temperatures, and durations were then analyzed. The recoverable component, R, of degradation was found to increase when the magnitudes of the applied stress voltage and temperature were increased. Moreover, the R was reduced when the recovery time was increased for a single run. In contrast, the R increased when the recovery time was increased for multiple runs. The normalized R of the simulated device was found to decrease by 0.7% and to increase by 7% with respect to the shortest recovery duration for a single run and for multiple runs, respectively. In addition, we measured the effects of equivalent oxide thickness (EOT) on the R and found that, in our study, the R for a transistor with a smaller EOT exhibited a substantial increase of 84% compared with that for a transistor with a larger EOT. These characteristics of the R of dynamic NBTI could be explained from the perspectives of the reaction–diffusion (R–D) model and hole-trapping mechanism. The results suggested that the underlying connection between these two mechanisms was the interface trap concentration, which represents the permanent components in both mechanisms.

Insight into the multicomponent nature of negative bias temperature instability

A novel measurement technique is used to extract two physically distinct “permanent” (long lived on our experimental time scale, ≤12 000 s) and one recoverable charge components of the negative bias temperature instability in p-channel metal–oxide–semiconductor field effect transistors under inversion and n-channel devices under accumulation. The results suggest that the permanent components are present in both cases, while there is little, if any, recoverable charge present in the case of the n-channel device. A physical explanation is provided involving the band energy diagram to explain these observations.

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔVth caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

The operation of germanium (Ge) dual-gated junctionless p-channel field-effect transistors (DG JL pFETs) is demonstrated. The top-gated hole mobility is approximately 120 cm2·V-1·s-1, which is close to the bulk mobility of p-type Ge with a doping concentration of 1019 cm-3. The mobility has a weak hole density dependence and increases by applying a negative bottom gate voltage. In addition, simple analytical expressions for both the current–voltage characteristics and the threshold voltage in the linear region of the DG JL pFET are described. The result shows that normally-off Ge DG JL pFETs are achievable. Furthermore, the threshold voltage variation due to the random dopant number fluctuations in the channel is also discussed, which indicates that it can be reduced by decreasing the Ge and oxide thicknesses.

Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

The operation of germanium (Ge) dual-gated junctionless p-channel field-effect transistors (DG JL pFETs) is demonstrated. The top-gated hole mobility is approximately 120 cm2·V-1·s-1, which is close to the bulk mobility of p-type Ge with a doping concentration of 1019 cm-3. The mobility has a weak hole density dependence and increases by applying a negative bottom gate voltage. In addition, simple analytical expressions for both the current–voltage characteristics and the threshold voltage in the linear region of the DG JL pFET are described. The result shows that normally-off Ge DG JL pFETs are achievable. Furthermore, the threshold voltage variation due to the random dopant number fluctuations in the channel is also discussed, which indicates that it can be reduced by decreasing the Ge and oxide thicknesses.

Fabrication and Electrical Properties of Thermally Oxidized p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on 4H-SiC C-Face

Fabrication and Electrical Properties of Thermally Oxidized p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on 4H-SiC C-Face

Fabrication and Electrical Properties of Thermally Oxidized p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on 4H-SiC C-Face

We characterized the SiO2/SiC interface by capacitance–voltage (C–V) measurement in order to obtain p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on the 4H-SiC(0001̄) C-face. Wet gate oxidation was preferable for both n- and p-type MOS capacitors, but p-type MOS interface properties were inferior to those of n-type MOS capacitors. The cause of the large flat-band shift for the p-type sample was discussed on the basis of C–V measurements by the light illumination technique. We also investigated the influence of the high-temperature annealing process after gate oxidation on the MOS interface properties. The p-type MOS interface was more sensitive to the annealing process than the n-type MOS interface. We fabricated 4H-SiC C-face p-channel MOSFETs by wet gate oxidation and low-temperature postdeposition annealing in He–H2 ambient. The normal FET operation was accomplished on the 4H-SiC C-face for the first time. Those devices, however, indicated low channel mobility and large threshold voltage.

Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance

Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance

Characteristics of 4H-SiC n- and p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ion-Implanted Buried Channel

We investigated the electrical characteristics of 4H-SiC n- and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with ion-implanted buried channels. The effects of the impurity concentrations of the buried channel (Cbc) on their electrical characteristics were quite different. In the case of n-channel MOSFETs, the threshold voltage decreased and the channel mobility increased with an increase in Cbc. On the other hand, in the case of p-channel MOSFETs, the threshold voltage and the maximum channel mobility were almost independent of Cbc. The conduction mechanism of the buried-channel MOSFETs is discussed in this paper.

Characteristics of 4H-SiC n- and p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ion-Implanted Buried Channel

Characteristics of 4H-SiC n- and p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ion-Implanted Buried Channel

Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance

This paper presents a two-stage, two-phase, p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with special two-step clocks for ripple reduction. The ripple voltage can be reduced by adjusting the overdrive voltage during charge transfer. The charge pump including the circuit of the proposed clocks and 5 pF boosting capacitance was fabricated using 0.35 µm complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of 0.182 mm2. With the new clock scheme, high voltage gain and driving capacity without overstress of the transistors are preserved. The experimental results reveal that the output voltage ripple is reduced from 23.2 to 12.8 mV for an output current of 36 µA at a frequency of 10 MHz and a supply voltage of 1.8 V, which indicates a 45% ripple reduction without increasing filtering capacitance.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2Interfacial Layers

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2 Interfacial Layers

We have successfully fabricated high hole mobility Ge p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs) with GeO2/Ge formed by direct thermal oxidation, which can yield a significantly low interface trap density (Dit). Al2O3 films are employed as capping layers for protecting the GeO2/Ge MOS interfaces during the MOSFET fabrication processes. The source/drain (S/D) regions are formed by boron ion implantation in a self-align way with Al gate metal. The good MOS interface properties are found to be maintained even after the activation annealing at temperatures sufficient for obtaining the excellent junction properties. The fabricated MOSFETs exhibit high source and drain on/off current ratios of 105–104 and a high peak hole mobility of 575 cm2 V-1 s-1 at maximum, both of which are attributable to the excellent GeO2/Ge MOS interface properties. The effects of the substrate impurity concentration and the thickness of GeO2 on the hole mobility are examined. It is found from the results for different substrate impurity concentrations that the universal curve between hole mobility and the effective field Eeff holds for η= 1/3. We also investigate the impact of the oxidation temperature dependence on hole mobility in order to examine the scattering mechanism limiting the mobility of GeO2/Ge interfaces through the modulation of the MOS interfaces by changing oxidation temperature. It is found that the mobility in low-temperature and low-surface carrier density (Ns) regions is well corrected with Dit evaluated from S factors in MOSFETs. In addition, it is revealed from transmission electron microscopy analyses that the interface roughness between GeO2 and Ge is reduced with increasing oxidation temperature. From these experimental results, the higher mobility of GeO2/Ge p-MOSFET at higher oxidation temperatures can be explained by the reduction in the density of Coulomb scattering centers and surface roughness at elevated Ge oxidation temperatures.