Oxide Semiconductor Field Effect Transistor Research Articles

Blocker tolerant cascode LNA for Wifi & IoT applications

SummaryWithin the domain of contemporary wireless communication systems, crafting Low‐Noise Amplifiers (LNA) holds a pivotal significance in achieving heightened signal sensitivity and comprehensive system efficacy and suppresses noise contributions from subsequent stages. Additionally, the low noise figure (NF) and high gain are critical LNA performance parameters in portable applications. Normally, LNA contains issues in noise performance, amplification, bandwidth, gain, and stability. To overcome these challenges, there must be a proper selection of transistors, harmonious impedance calibration, bias optimization, and circuit fine‐tuning. Moreover, metal oxide semiconductor field effect transistors (MOSFETs) are a popular choice in LNA design because of their excellent noise performance, high input impedance, complementary metal‐oxide semiconductor (CMOS) integration capabilities, low power operation, and suitability for a wide range of frequency applications. Through simulation and iterative enhancement, the LNA showcases remarkable Noise Figure, amplification, and linearity over a designated frequency span. This creation contributes to the advancement of radio frequency (RF) circuitry by designing an approach for LNA crafting that harmonizes conflicting prerequisites and unveils effective noise mitigation tactics. The outcomes emphasize the importance of a deliberated circuit architecture and parameter adjustment in accomplishing superlative LNA capabilities, rendering it fit for assimilation into diverse communication systems that demand minimal noise and heightened sensitivity.

Calculating and analyzing time delay in zigzag graphene nanoscrolls based complementary metal-oxide-semiconductors

Graphene Nano Scrolls (GNSs) and Zigzag graphene nanoscrolls (ZGNSs) are semi-one-dimensional materials with exceptional electrical and optical properties, making them attractive to be used in nanoelectronics and complementary metal–oxide–semiconductor (CMOS) technology. With in CMOS device technology, time delay is a crucial issue in the design and implementation of CMOS based ZGNSs. Current paper focus is on ZGNSs application in the channel area of metal–oxide–semiconductor field-effect transistors (MOSFETs) in CMOS technology. We studied analytically, the importance of different parameters on time delay reduction, resulting in faster switching and higher frequency in integrated circuits (ICs). The results of this research demonstrates that, the ZGNS-based CMOS proves considerable variations in the current due to the geometrical parameters, such as chirality number, channel length, and nanoscroll length which can be engineered to produce faster ICs.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Tunneling field-effect transistors with two-dimensional BiN as the channel semiconductor

The lack of suitable channel semiconductor materials has been a limiting factor in the development of tunneling field-effect transistor (TFET) architectures due to the stringent criteria of both air stability and excellent gate-tunable electronic properties. Here, we report the performance limits of sub-10-nm double-gated monolayer (ML) BiN TFETs by utilizing first-principles quantum-transport simulations. We find that ML BiN possesses an indirect bandgap of 0.8 eV and effective masses of 0.24m0 and 2.24m0 for electrons and holes, respectively. The n-type BiN TFETs exhibit better performance than the p-type ones, and the on-state current can well satisfy the requirements of the International Roadmap for Devices and Systems for both high-performance and low-power standards. Notably, we find that the BiN TFETs exhibit distinguished gate controllability with an ultra-low subthreshold swing below 60 mV/decade even with a small gate length of 6 nm, which is superior to the existing field-effect transistors, such as black phosphorus TFETs, GeSe TFETs, and BiN metal–oxide–semiconductor field-effect transistors. Furthermore, the BiN TFETs are endowed with the potential to realize high switching speed and low-power consumption applications because of their extremely short delay time and ultra-low power-delay product. Our results reveal that the ML BiN is a highly competitive channel material for the next-generation TFETs.

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs due to Power Cycling Tests

Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg >> Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Performance Improvement of a ZnGa2O4 Extended-Gate Field-Effect Transistor pH Sensor.

ZnGa2O4 sensing films were prepared using an RF magnetron sputtering system and connected to a commercial metal oxide semiconductor field-effect transistor (MOSFET) as the extended-gate field-effect transistor (EGFET) to detect pH values. Experimental parameters were adjusted by varying the oxygen flow rate in the process chamber to produce ZnGa2O4 sensing films with different oxygen ratios. These films were then treated in a furnace tube at an annealing temperature of 700 °C. The sensitivity and linearity of the constant current mode and the constant voltage mode were measured and analyzed in the pH range of 2-12. Under the deposition conditions with an oxygen ratio of 6%, the sensitivity reached 23.14 mV/pH and 33.49 μA/pH, with corresponding linearity values of 92.1 and 96.15%, respectively. Finally, the sensing performance of the ZnGa2O4 EGFET pH sensor with and without annealing processes was analyzed and compared.

Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs

We investigated the effects of the column length and fabrication method of the superjunction (SJ) structure on the reverse recovery characteristics of 1.2 kV silicon carbide (SiC) SJ metal–oxide–semiconductor field-effect transistors (MOSFETs). The voltage slope (dV/dt) and reverse recovery current slope (dir/dt) values during the reverse recovery of the SJ-MOSFETs with the SJ structure formed by Aluminum (Al) ion implantation were comparable to the values of MOSFETs without SJ structure at room temperature (RT), but they increased markedly with temperature. This is caused by the reduced p-column carrier concentration at RT during short recovery transient time due to the deep hole trap (DI center) introduced by ion implantation. At 175 °C, a softer reverse recovery waveform was obtained by shortening the SJ columns. Besides, Al ion implanted SJ-MOSFETs exhibited a weaker current dependence of the reverse recovery charge Qrr at 175 °C indicating a lower carrier injection level compared to the SJ-MOSFETs with the SJ structure formed by trench formation and epitaxial growth. This is caused by the short carrier lifetime of the SJ columns due to the Al ion implantation defects. The short and Al ion implanted SJ columns are effective for soft reverse recovery characteristics in SiC-SJ-MOSFETs.

Revolutionizing Technology with Spintronics: Devices and Their Transformative Applications

The scaling of metal oxide semiconductor field effect transistors (MOSFETs) for data storing and logic circuit operation has reached a critical point, beyond which further scaling poses various secondary issues. These problems include short channel effects, hot carrier effects (HCEs), and reliability concerns. However, a promising alternative called spintronics has recently emerged as a highly exciting technology. Spintronics considers both the charge and spin of electrons in device operations and offers superior properties compared to MOSFETs.Researchers have reported numerous spintronics devices that exhibit significant potential in memory and logic circuits when integrated with complementary metal oxide semiconductor (CMOS) technology. These devices not only possess excellent scalability but also consume less power than MOSFETs at the nano-scale level. This article aims to provide a comprehensive review of the current state, future prospects, and challenges associated with spintronics devices.

Research and analysis of electromagnetic interference of a motor drive control system based on PMSM with SiC MOSFET for new energy electric vehicles

Sustainable development in the 21st century faces significant challenges due to finite reserves of fossil fuels and environmental pollution. In the context of new energy electric vehicles (NEEVs), the wide-bandgap semiconductor known as the silicon carbide–metal oxide–semiconductor field-effect transistor (SiC MOSFET) and the permanent magnet synchronous motor (PMSM) have emerged as advantageous sources. However, the use of these components gives rise to electromagnetic interference (EMI) issues, which impede the achievement of electromagnetic compatibility (EMC) standards in the motor drive control system. This paper aims to elucidate the generation mechanism, propagation path, and test infrastructure of EMI. Furthermore, it proposes a system-level conducted EMI equivalent circuit model for the motor drive control system, encompassing the power battery pack, busbar cable, LISN, three-phase inverter, and PMSM. Building upon this foundation, the principles for suppressing and optimizing EMI noise are discussed. The paper concludes with the validation of simulations and experimental results, which demonstrate the effectiveness of the proposed approach. It is anticipated that professionals with an interest in the field of EMI/EMC will find this paper to be of both theoretical and practical importance.

2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation

To process 1-bit of information the small supply voltage (Vdd) and minimal leakage current are needed for transistors. Subthreshold swing (SS) of 60 mV/dec at 300 K is the basic bottleneck in metal oxide semiconductor field effect transistors. DFT in QuantumATK R-2020.09 was used to study Si0.8Ge0.2 band structure and band gap. A p-type tunnel field effect transistor (PTFET) was modeled employing the dual gate concept. Top gate has two metals; source and counter doped pocket are Si0.8Ge0.2. According to the proposed device simulation, the proposed device is showing excellent thermal stability for large on-current (Ion), weak off-current (Ioff), and weak ambipolar current (Iambi) at different temperatures. The proposed device achieves the Ion of 72.44 µA/µm and 3.2 µA/µm at supply voltage of −1 V and −0.5 V, respectively. At −0.5 V of Vdd, current ratio of Ion/Ioff is more than 1012, so device can be used for low power applications.

Comparative Study of Different High Voltage Switches Used in Pulsed High Voltage Application

High-voltage switches play a crucial role in pulsed power applications, where the efficient and reliable control of highvoltage pulses is required. This study aims to compare different types of high-voltage switches commonly used in pulsed power systems including electromechanical switches, vacuum switches, gas-filled switches, triggered spark gaps and solidstate switches. The comparison study focuses on key performance parameters such as voltage handling capability, current carrying capacity, turn-on time, and repetition rates are considered to provide a comprehensive study and analysis of the switch’s suitability for different pulsed power applications. Gas-filled switches such as spark gaps, thyratrons and ignitrons have been used in pulsed power systems due to their high voltage handling capability and low switching losses. However, they suffer from a limited lifetime and require maintenance and periodic replacement. Solid-state switches, i.e. Silicon-Controlled Rectifiers (SCRs), Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) offer advantages in terms of longevity, reliability, and reduced maintenance. However, they have limitations in high-voltage applications and exhibit higher switching losses. The findings of this comparison study will assist researchers, engineers, and system designers in selecting the most appropriate high-voltage switch for pulsed power applications, considering the specific requirements and constraints of the system. This will ultimately contribute to the advancement and optimization of pulsed power technologies across a wide range of scientific, industrial, and strategic applications.

Impact of water vapor annealing treatments on Al2O3/diamond interface

Our group developed the first inversion-type p-channel diamond metal–oxide–semiconductor field-effect transistor, which featured normally off properties by employing water vapor annealing treatments for the oxygen-terminated diamond surface. Despite the comprehensive device-grade characterization, the impact of water vapor annealing treatments on the Al2O3/diamond interface has not been investigated in detail. In this work, we fabricated four diamond metal–oxide–semiconductor (MOS) capacitors without and with water vapor annealing treatments for various times of 30 min, 1 h, and 2 h and conducted the cycle capacitance–voltage (C–V) and simultaneous C–V measurements. The large cycle C–V shift existed in the sample without water vapor annealing treatment, whereas it was significantly suppressed by water vapor annealing treatments, indicating the effective passivation of the traps with long time constants. The simultaneous C–V results showed a similar trend that the frequency dispersion of the simultaneous C–V was dramatically reduced with water vapor annealing treatments, and the interface quality of Al2O3/diamond had a slight dependence on the water vapor annealing times. Based on simultaneous C–V measurements, the interface state density (Dit) at an energy level of 0.2–0.6 eV from the valence band edge of diamond was extracted for the different MOS capacitors. The Dit was reduced by one order of magnitude with water vapor annealing treatments, and it almost did not change with the water vapor annealing times. Besides, the flat band voltage shift and effective fixed charge were also dramatically reduced by water vapor annealing. The possible physical reason for the interface improvement by water vapor annealing treatments was discussed.

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition

Effect of Metal Oxide Semiconductor Field-Effect Transistor Output Parasitic Capacitance on Efficiency in Full-Bridge LLC DC/DC Converters.

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance (Coss) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.