Overlay Control Research Articles

Advanced metrology needs for nanoelectronics lithography

The semiconductor industry has exploited productivity improvements through aggressive feature size reduction for over four decades. While enormous effort has been expended in developing the optical lithography tools to print ever finer features, significant advances have also been required to measure the printed features. In this article we will discuss the current state of the art in the metrology for measuring critical dimensions of printed features for scanning electron microscopy and atomic force microscopy, and describe work at the National Institute of Standards and Technology advancing these tools as well as exploratory work on two new promising techniques, scatterfield microscopy and small angle X-ray scattering. Line width roughness critical dimension and overlay metrology and control are two of the most significant industry needs mentioned in the International Technology Roadmap for Semiconductors (2005). To cite this article: S. Knight et al., C. R. Physique 7 (2006).

TCP-Westwood Low-Priority for Overlay QoS Mechanism

An overlay traffic control is a way to provide flexible and deployable QoS mechanisms over existing networks, such as the Internet. While most of QoS mechanisms proposed so far require router supports, overlay QoS mechanisms rely on traffic control at transport layer without modifying existing routers in the network. Thus, traffic control algorithms, which are implemented at traffic sources or PEPs (Performance Enhancement Proxies), play a key role in an overlay QoS mechanism. In this paper, we propose an end-to-end prioritization scheme using TCP-Westwood Low-Priority (TCPW-LP), a low-priority traffic control scheme that maximizes the utilization of residual capacity without intrusion on coexisting foreground flows. Simulation and Internet measurement results show that TCPW-LP appropriately provides end-to-end low-priority service without any router supports. Under a wide range of buffer capacity and link error losses, TCPW-LP appropriately defers to foreground flows and better utilizes the residual capacity than other proposed priority schemes or even TCP Reno.

Improved Hepatocyte Excretory Function by Immediate Presentation of Polarity Cues

Liver tissue constructs with excretory function are crucial to developing realistic hepatocyte models for engineering effective bioartificial liver-assisted devices and for modeling the in vivo tissue. Current hepatocyte in vitro models suffer from limited or inefficient hepatocyte repolarization, which results in poor removal of xenobiotics and other waste products from the cells. We hypothesized that the temporal and spatial presentation of the cell matrix and cell-cell contacts as polarity cues would be important to define the axis of polarization to improve the excretory function of hepatocytes. The spatial presentation of polarity cues can be best achieved with sandwich configuration. We improve the temporal presentation of polarity cues by introducing the collagen overlay immediately in synchrony with cell-cell contacts instead of after 24 h in conventional sandwich culture. We demonstrate that the immediate presentation of the collagen matrix overlay enhances the formation of apicobasolateral domains, tight junctions, and the recovery of the functional activity of 2 canalicular transporters, the multidrug resistance-associated protein (Mrp2) and P-glycoprotein (P-gp) at 48 h of culture, and enhances the albumin secretion, urea production, and 7-ethoxyresorufin-O-deethylation cytochrome P450 activities of hepatocytes over 14 days of culture as compared to the 24-h overlay controls. The improvement in the excretory function of hepatocytes for the removal of waste products deleterious to cells may improve the functional maintenance and the in vivo fidelity of tissue-engineered liver constructs.

Run-to-Run Overlay Control of Steppers in Semiconductor Manufacturing Systems Based on History Data Analysis and Neural Network Modeling

This paper presents a new run-to-run control scheme to reduce overlay misalignment errors in steppers and demonstrates the feasibility of the scheme by real-time experimental tests. The overlay misalignment error mainly depends on two factors: one is the internal dynamics of photo processes and steppers and the other is the process history of lots, such as base equipment and reticles. Based on these observations, a new control scheme was designed to find the stepper inputs minimizing the misalignment errors based on history data analysis and neural network models. Moreover, we demonstrated that the proposed control scheme reduces the spec-out ratios as well as the number of engagements of the send-ahead wafer process, which thereby results in the increase of product yield in semiconductor manufacturing.

Optical network control overlay using silicon VOA arrays

A silicon-based variable optical attenuator (VOA) is used to overlay optical control data on an underlying high-speed optical data channel. We demonstrate experimentally the addition of a 10.7-MHz (5 Kb/s) control subcarrier with <1-dB penalty to a high-speed channel (500 Mb/s) and quantify the penalty versus control data rate. The modest modulation bandwidth of the VOA enables control subcarriers at frequencies sufficiently high to avoid gain saturation-induced crosstalk in erbium amplifiers, while using the same devices required for channel gain equalization or power control. At OC-192 data rates, we predict that control-channel data rates of 10 Kb/s can be tolerated with <0.5-dB penalty.

Opportunities and Challenges in Immersion Lithography

At IMEC, one of the first full field 193nm immersion scanners has been installed, i.e. a XT:1250Di with maximum NA=0.85. Immersion tools are expected to show the same stability and control as the equivalent dry systems. Therefore CDU, focus and overlay control are being evaluated. New aspects arise with respect to photoresist processing and defectivity due to the interaction with water, such as leaching and water uptake. Resists need to be optimized for this, and in the mean time immersion top coats are introduced to overcome these issues. These top coats prevent leaching of resist components, but can show new problems such as the occurrence of a mixing layer with the resist or a soaking fingerprint. Resolution enhancement techniques need to be reconsidered taking into account the better process latitudes and imaging performance caused by immersion. As immersion will lead to the introduction of NA's larger than 1, simulation studies are started to understand the impact of high incident angles on the mask level such as the effect of mask topography and polarization.

Run-to-run control and performance monitoring of overlay in semiconductor manufacturing

In the manufacture of semiconductor products, overlay is one of the most critical design specifications. Overlay is the position of a pattern relative to underlying layers, and overlay control largely determines the minimum feature size that may be incorporated into semiconductor device designs. Overlay control must be performed on a run-to-run basis, i.e. at the end of a run when product characteristics are available, because they cannot be directly measured during a run. In this research a process model and a run-to-run control scheme was developed for overlay control, based on linear model predictive control, and successfully implemented in a commercial facility. Performance monitoring of the closed-loop process was also carried out.

Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing

To enhance the resolution and alignment accuracy in semiconductor manufacturing, it is important to measure overlay errors and control them into the tolerances by removing assignable causes. A number of related studies have been done to examine the factors causing the overlay errors, to propose mathematical models and to develop overlay error control methods. However, the involved sampling strategies received little attention. This study aimed to propose specific designs of sampling patterns effectively to measure and compensate for overlay errors within the limited number of samples in practice. To verify the validity of the proposed approach, the sampling strategies were compared using empirical data from a wafer fabrication facility. The proposed sampling patterns had a higher goodness of fit for the overlay model and lower residuals after compensation. This paper concludes with our findings and discussions on further research.

RUN-TO-RUN CONTROL AND PERFORMANCE MONITORING OF OVERLAY IN SEMICONDUCTOR MANUFACTURING

In the manufacture of semiconductor products, overlay is one of the most critical design specifications. Overlay is the position of a pattern relative to underlying layers, and overlay control largely determines the minimum feature size that may be incorporated into semiconductor device designs. Overlay control must be performed on a run-to-run basis, i.e. at the end of a run when product characteristics are available because they cannot be directly measured during a run. In this research a process model and a run-to-run control scheme was developed for overlay control, based on linear model predictive control (LMPC), and successfully implemented in a commercial facility. Performance monitoring of the closed-loop process was also carried out.

Optimization of Sample Plan for Overlay and Alignment Accuracy Improvement

The overlay control requirement for a sub-0.15 µm design rule device is nominally less than 40 nm. To meet this demand, every factor known to affect the overlay budget should be analyzed in detail and corrected as much as possible. One of the major causes degrading the overlay budget is the nonoptimized wafer sample plan. Compensated but undercorrected overlay errors fitted as linear terms can be amplified in case of using improper sample plan (e.g., an asymmetric plan). In this study, we investigated the sample plan dependency of global alignment repeatability and overlay measurement accuracy. The achievement of better alignment repeatability is critical for improving not only in-wafer overlay but wafer-to-wafer overlay control. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected for global alignment use. Several sample plans which are limited to the symmetric group (i.e., translation, inversion, rotation and symmetric), are tested. The criteria for selecting the optimum sample plan were the residuals and linear-term reproducibility, both of which are significantly affected by raw data noise. Raw data variations include stage positioning errors and process-induced alignment signal abnormality. From among the candidates, we determined an optimal sample plan which leaves the least residuals and exhibits repeatability as good as that in full chip measurement. Similar results could be obtained for an overlay sample plan.

Status and future of X-ray lithography

X-ray lithography is relatively mature, and may be used to manufacture complex integrated circuits at 130 nm ground rules and smaller. Overlay and critical dimension control for 180 nm ground rules have been demonstrated with synchrotron-based x-ray lithography. Significant engineering challenges remain in making x-ray masks for 180 nm and smaller ground rules. Extendibility of x-ray lithography to 100 nm ground rules and below will require ≤20 μm gaps and careful mask bias optimization.

Space-charge limitations to throughput in projection electron-beam lithography (SCALPEL)

Coulomb interactions in high-throughput charged particle lithography systems lead to an uncorrectable image blur, and can also results in image placement errors. Throughput is ultimately limited by the increasing loss of process latitude with increasing beam current, or by the loss of critical dimension or overlay control due to placement errors. We previously developed an analytical model of the stochastic space-charge induced beam blur for our SCALPEL (SCattering with Angular Limitation Projection Electron Lithography) system, and used it to optimize the design of our experimental tool; principally by constraining the column length and optimizing the numerical aperture to achieve the best balance between electron-optical aberrations and the stochastic blur. We have attempted to validate this model with experimental measurements. We have also begun to quantify pattern distortions due to the global space-charge effects. Preliminary measurements show dose latitudes of ∼ 15%, consistent with a total blur of ∼ 150 nm, and a space-charge component no larger than 30 nm. No evidence for current dependent intrafield distortions has been observed.

Evolution Strategies for Mobile Telephony Employing Multiple Coexisting Technologies

In many countries, the analogue Advanced MobilePhone System (AMPS) is progressively being replaced bydigital technologies, with the intention of maximizingcapacity and service quality. This paper considers strategies for the evolution of mobiletelephony services, employing several coexistingmultiple access technologies, such as Code DivisionMultiple Access (CDMA) and Global System for Mobile(GSM), in recovering the spectrum previously used byanalogue technologies such as AMPS. We propose partialspectral overlay and interference control strategies forCDMA systems overlaying AMPS and GSM systems, to provide smooth transition paths for introducingthe CDMA technology, and we show that these overlaystrategies lead to significant increases in overallnetwork capacity.

Compatibility between two SR steppers

Two SR steppers, SS-1[1] and SS-2, are used at the NTT SR facility to accelerate the development of LSIs with a feature size of 0.2 microns or less. This paper presents the compatibility of the two SR steppers focusing on overlay accuracy. For stepper to stepper overlay, repeatability and offset controllability are the important factors. The stand-alone overlay repeatability of ±30nm, and offset control resolution of 10nm are achieved. The difference of run-out error between two beamlines, which have an adverse affect on compatibility, are measured. It is less than 60nm in 18mm square. The influence of chucked wafer flatness to overlay accuracy is clarified by experiments and simulations. The overlay accuracy of 60 nm(3 σ) for the two SR steppers is obtained by double exposure methods using the same mask and alignment marks formed by a photo stepper. These two steppers are now being applied to test device fabrication.

Fabrication of fully scaled 0.5-μm n-type metal–oxide semiconductor test devices using synchrotron x-ray lithography: Overlay, resist processes, and device fabrication

Functional, fully scaled n-type metal–oxide semiconductor (NMOS) circuits with 0.5-μm ground rules have been fabricated using synchrotron radiation x-ray lithography for all device levels. The exposures were done at the vacuum ultraviolet storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The system is capable of step-and-repeat exposures covering 125-mm wafers. The mask and wafer are held in a near-vertical plane and a scanning dark-field alignment technique is used to register mask to wafer with a proximity gap of 40 μm. A scanning mirror in the beamline sweeps the x-ray beam up and down over the exposure area to achieve uniform exposure over the 25×25 mm2 exposure field used for this experiment. Exposures were done in 20 Torr of helium to provide cooling for the mask. Both positive and negative tone single-layer resists were used. The mask set consists of four light-field masks patterned on silicon substrates with electroplated gold absorbers; patterns were written by a vector scan electron beam lithography system. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay and linewidth control. The repeatability of the alignment and the overall level-to-level overlay are described. Characteristics of the fabricated devices are also presented.

Lithography issues in fabricating high-performance sub-100-nm channel metal–oxide semiconductor field effect transistors

Specific issues related to achieving high device performance in extremely small channel length field effect transistor circuits are discussed. Ultrahigh resolution electron beam lithography is needed to obtain the ultrashort channels which are key for fast devices, and for the important gate area, double‐layer poly(methylmethacrylate) for lift‐off of a metal reactive ion etching mask has proven to be a suitable technique. Good level to level overlay and dimensional control in the contact process allow miniaturization of all device elements, in particular, reduction of the distance between source/drain contacts and optimization of the contact size and geometry. These are key factors in minimizing parasitic effects. The design considerations are discussed and the fabrication techniques are described which resulted in devices with a maximum measured transconductance of 910 mS/mm at 77 K for a 70‐nm gate device, exhibiting the clearest evidence so far for electron velocity overshoot, and unloaded ring oscillators with 13‐ps switching time per stage.

Resolution limit of E-beam direct writing technology

Abstract The resolution limit of E-beam direct writing technology for ultimately small VLSI fabrication was discussed, from the view point of resist resolution and accuracy in overlay and linewidth control. 2-layer resist system composed of newly developed Silicone-based Negative Resist (SNR) realizes nanometer structure fabrication with high aspect ratio and large dosage margin by negative type E-beam exposure. An overlay accuracy less than 20 nm is achieved by new mark detection system, and the simulation studies indicate the linewidth control less than 20 nm by using multi-layer resist system. These results suggest the lithographic possibility of VLSI with a ground rule of 0.1 μm.

IBM system designs from scratch: Electronics p. 93 (14 July 1981)

Two SR steppers, SS-1[1] and SS-2, are used at the NTT SR facility to accelerate the development of LSIs with a feature size of 0.2 microns or less. This paper presents the compatibility of the two SR steppers focusing on overlay accuracy. For stepper to stepper overlay, repeatability and offset controllability are the important factors. The stand-alone overlay repeatability of ±30nm, and offset control resolution of 10nm are achieved. The difference of run-out error between two beamlines, which have an adverse affect on compatibility, are measured. It is less than 60nm in 18mm square. The influence of chucked wafer flatness to overlay accuracy is clarified by experiments and simulations. The overlay accuracy of 60 nm(3 σ) for the two SR steppers is obtained by double exposure methods using the same mask and alignment marks formed by a photo stepper. These two steppers are now being applied to test device fabrication.

Control Methods in Subsurface Map Construction

Problems of control in the preparation of subsurface maps can be solved most effectively and efficiently in virtually all circumstances by the method of cross-section control, allied to that of overlay control. Applications in subsurface work in Iraq, Qatar, and Abu Dhabi demonstrate this approach. Maps are two-dimensional representations of three-dimensional situations. Cross sections are valuable in constructing structure contour maps from well data, especially in complex and steeply dipping structures. Cross sections based on well data are effective controls in thickness map construction and are invaluable corrective and controlling aids in preparing maps where thicknesses are affected tectonically.