Lithography issues in fabricating high-performance sub-100-nm channel metal–oxide semiconductor field effect transistors

Abstract

Specific issues related to achieving high device performance in extremely small channel length field effect transistor circuits are discussed. Ultrahigh resolution electron beam lithography is needed to obtain the ultrashort channels which are key for fast devices, and for the important gate area, double‐layer poly(methylmethacrylate) for lift‐off of a metal reactive ion etching mask has proven to be a suitable technique. Good level to level overlay and dimensional control in the contact process allow miniaturization of all device elements, in particular, reduction of the distance between source/drain contacts and optimization of the contact size and geometry. These are key factors in minimizing parasitic effects. The design considerations are discussed and the fabrication techniques are described which resulted in devices with a maximum measured transconductance of 910 mS/mm at 77 K for a 70‐nm gate device, exhibiting the clearest evidence so far for electron velocity overshoot, and unloaded ring oscillators with 13‐ps switching time per stage.