Optimization of Sample Plan for Overlay and Alignment Accuracy Improvement

Abstract

The overlay control requirement for a sub-0.15 µm design rule device is nominally less than 40 nm. To meet this demand, every factor known to affect the overlay budget should be analyzed in detail and corrected as much as possible. One of the major causes degrading the overlay budget is the nonoptimized wafer sample plan. Compensated but undercorrected overlay errors fitted as linear terms can be amplified in case of using improper sample plan (e.g., an asymmetric plan). In this study, we investigated the sample plan dependency of global alignment repeatability and overlay measurement accuracy. The achievement of better alignment repeatability is critical for improving not only in-wafer overlay but wafer-to-wafer overlay control. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected for global alignment use. Several sample plans which are limited to the symmetric group (i.e., translation, inversion, rotation and symmetric), are tested. The criteria for selecting the optimum sample plan were the residuals and linear-term reproducibility, both of which are significantly affected by raw data noise. Raw data variations include stage positioning errors and process-induced alignment signal abnormality. From among the candidates, we determined an optimal sample plan which leaves the least residuals and exhibits repeatability as good as that in full chip measurement. Similar results could be obtained for an overlay sample plan.