Design Overhead Research Articles

Making Aging Useful by Recycling Aging-induced Clock Skew

Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this article, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating and recycling these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its effective performance degradation due to aging can be tolerated. On average, 21.21% aging tolerance can be achieved with insignificant design overhead. Moreover, we employ V th assignment on clock buffers to further tolerate the aging-induced degradation of logic networks. When V th assignment is applied on top of aforementioned aging manipulation, the average aging tolerance can be enhanced to 29.15%.

An Enhanced Logic Encryption Method with a Fully Correlated Key Interdependency Block

Logic encryption, as a hardware security technique, can protect integrated circuits (ICs) by inserting additional gates. The inserted gates guarantee that predefined outputs are only generated when correct key inputs are provided, preventing IC counterfeiting, intellectual property (IP) theft, and IC overproduction. To evaluate the logic encryption’s robustness, two major criteria are usually utilized, which are (1) the interdependency between the keys and (2) the output corruption against attacks, including path sensitization attack, SATbased attack, hill-climbing attack, etc. However, the majority of existing logic encryption methods emphasize one criterion over the other. In this paper, an enhanced logic encryption method with a fully correlated key interdependency block is proposed. The method enhances the interdependency of keys and determines the locations of key-gates utilizing a rare node analysis method. Experimental results validate that the proposed method can withstand path sensitization attack and ensure 50% Hamming distance with reasonable design overheads.

IP Core Steganography for Protecting DSP Kernels Used in CE Systems

Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel ‘IP core steganography’ methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented ‘IP core steganography’ methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary’s perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a ‘thresholding’ parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.

Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses

Outsourcing data to a third-party cloud provider has become quite common with the increasing use of cloud computing. This brings convenience, as well as the concern for data security and privacy. It is believed that data encryption alone is often not enough to protect users' privacy from the cloud provider. According to previous work, the sequence of storage locations accessed by the client can leak up to 90% of the sensitive information, even with data encrypted. In this context, Oblivious RAM (ORAM) is proposed. ORAM algorithms allow the client to hide its access pattern from the service provider while introducing a lot of extra operations. Among all the prototypes, Path ORAM is one of the most promising designs. However, there are still redundant memory accesses that can be removed without harming the security of traditional ORAM as we observed. We came up with three optimization techniques, including path merging, ORAM request scheduling, and merging aware caching. We also propose a prefetching technique to further decreasing the access overhead. Moreover, we also illustrate the compatibility of Fork Path and some state-of-the-art Path ORAM optimizations. Compared to traditional Path ORAM approaches, our Fork Path ORAM can reduce overall performance overhead and power consumption of memory system by 65% and 44%, while the design overhead is trivial.

Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting

Hardware Trojan insertion and intellectual property (IP) theft are two major concerns when dealing with untrusted foundries. Most existing mitigation techniques are limited in protecting against both vulnerabilities. Split manufacturing is designed to stop IP piracy and integrated circuit (IC) cloning, but it fails at preventing untargeted hardware Trojan insertion and incurs significant overheads when high level of security is demanded. Built-in self-authentication (BISA) is a low-cost technique for preventing and detecting hardware Trojan insertion, but is vulnerable to IP piracy, IC cloning, or redesign attacks, especially on original circuitry. In this paper, we propose an obfuscated BISA technique that combines and optimizes both the techniques so that they complement and improve security against both vulnerabilities, while at the same time minimizing design overheads to the extent that the proposed method does not incur prohibitive cost for designs of industrial-level sophistication. Our evaluation on advanced encryption standard and data encryption standard cores shows that the proposed technique can reach security levels more than two times higher, satisfying all existing layout-based security metrics, while reducing overheads from hundreds of percents to less than 13% in power, 5% in delay, and zero percent in area, as compared to best reported performance in existing techniques.

Enabling Non-Hebbian Learning in Recurrent Spiking Neural Processors With Hardware-Friendly On-Chip Intrinsic Plasticity

Intrinsic plasticity (IP) is a non-Hebbian learning mechanism that self-adapts intrinsic parameters of each neuron as opposed to synaptic weights, offering complimentary opportunities for learning performance improvement. However, integrating IP onchip to enable per-neuron self-adaptation can lead to very large design overheads. This paper is the first work exploring efficient on-chip non-Hebbian IP learning for neural accelerators based on the recurrent spiking neural network model of the liquid state machine (LSM). The proposed LSM neural processor integrated with onchip IP is improved in terms of cost-effectiveness from both algorithmic and hardware design points of view. We optimize a baseline IP rule, which gives the state-of-the-art learning performance, to enable a feasible hardware onchip integration and further propose a new hardware-friendly IP rule SpiKL-IFIP. The hardware LSM neural accelerator with onchip IP is dramatically improved in area/power overhead as well as training latency with the proposed new IP rule and its optimized implementation. On the Xilinx ZC706 FPGA board, the proposed co-optimization dramatically improves the cost-effectiveness of on-chip IP. Self-adapting reservoir neurons using IP boosts the classification accuracy by up to 10.33% on the TI46 speech corpus and 8% on the TIMIT acoustic-phonetic dataset. Moreover, the proposed techniques reduce training energy by up to 49.6% and resource utilization by up to 64.9% while gracefully trading off classification accuracy for design efficiency.

Early‐stage microfluidic network design framework using graph sparsificiation based optimisation

Microfluidics has emerged as an effective technology for miniaturised manipulation and biochemical analysis. Recently, several physical design solutions for functional microfluidic chips have been presented. However, the commonly designed grid structure happens to be redundant with unnecessary channels, causing significant waste of expensive sample fluid. In this work, the authors propose an early stage microfluidic network design framework to sparsify the network topology and optimise network area overhead. Simulation results show that the proposed framework can generate the network to meet design constraints and reduce design overhead by almost 79.2% compared with prior works.

SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations

Most cipher implementations are vulnerable to a class of cryptanalytic attacks known as fault injection attacks. To reveal the secret key, these attacks make use of faults induced at specific locations during the execution of the cipher. Countermeasures for fault injection attacks require these vulnerable locations in the implementation to be first identified and then protected. However, both these steps are difficult and error-prone and, hence, it requires considerable expertise to design efficient countermeasures. Incorrect or insufficient application of the countermeasures would cause the implementation to remain vulnerable, while inefficient application of the countermeasures could lead to significant performance penalties to achieve the desired fault-attack resistance. In this paper, we present a novel framework called SAFARI for automatically synthesizing fault-attack resistant implementations of block ciphers. The framework takes as input the security requirements and a high-level specification of the block cipher. It automatically detects the vulnerable locations from the specification, applies an appropriate countermeasure based on the user-specified security requirements, and then synthesizes an efficient, fault-attack protected, RTL, or C code for the cipher. We take AES, CAMELLIA, and CLEFIA as case studies and demonstrate how the framework would explore different countermeasures, based on the vulnerability of the locations, the output format, and the required security margins. We then evaluate the efficacy of SAFARI in hardware and software to the design overhead incurred and the fault coverage.

S2Net: Preserving Privacy in Smart Home Routers

At present, wireless home routers are becoming increasingly smart. While these smart routers provide rich functionalities to users, they also raise security concerns. Although the existing end-to-end encryption techniques can be applied to protect personal data, such rich functionalities become unavailable due to the encrypted payloads. On the other hand, if the smart home routers are allowed to process and store the personal data of users, once compromised, the users’ sensitive data will be exposed. As a consequence, users face a difficult trade-off between the benefits of the rich functionalities and potential privacy risks. To deal with this dilemma, we propose a novel system named Secure and Smart Network (S2Net) for home routers. For S2Net, we propose a secure OS that can distinguish and manage multiple sessions belonging to different users. The secure OS and all the router applications are placed in the secure world using the ARM TrustZone technology. In S2Net, we also confine the router applications in sandboxes provided by the proposed secure OS to prevent data leakage. As a result, S2Net can provide rich functionalities for users while preserving strong privacy for home routers. In addition, we develop a crypto-worker model that provides an abstraction layer of cryptographic tasks performed by a heterogeneous multi-core system. The other important role of crypto-worker is to parallelize the computations in order to resolve the high computation cost of cryptographic functions. We report the system design of S2Net and the details of our implementation. Experimental results with benchmarks and real applications demonstrate that our implementation is capable of achieving high performance in terms of throughput while mitigating the overhead of S2Net design.

Robust Logic locking for Securing Reusable DSP Cores

A System on Chip (SoC) used in Consumer Electronics (CE) systems integrates a number of reusable Intellectual Property (IP) cores from digital signal processing (DSP), multimedia etc. However, these DSP based IP cores are susceptible to various hardware threats such as piracy, Trojan insertion, overbuilding and reverse engineering. Thus, security of DSP cores is very crucial. An IP core can be secured against aforementioned hardware threats by employing logic locking based security mechanisms. This paper presents a novel robust logic locking using hybrid locking cells for securing DSP cores. The proposed logic locking is based on a novel advanced encryption standard (AES) based reconfigurable hybrid locking cell architecture that ensures strong security against key sensitization, removal and SAT attacks. The strength of the proposed approach has been assessed in terms of probability of obtaining correct key of a locked design in exhaustive trials. Results of proposed work on DSP cores yielded higher logic locking strength and lower design overhead compared to recent prior works.

New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks

Finite state machine (FSM) is a critical part in digital processing devices used in Internet of Things (IoT) applications as it controls complete functionality of the device. The synthesis tool implements deterministic FSM by adding extra don’t care states/transitions during optimization. This additional insertion makes the FSM vulnerable to setup-time violation based fault injection (STVFI) and hardware Trojan attacks. The existing techniques are inefficient to completely mitigate these vulnerabilities and exhibit significant design overhead. Therefore, this paper presents a novel lightweight secure machine design technique that completely mitigates the vulnerabilities with minimum overhead. The paper first proposes a new metric to identify all types of vulnerable transitions (VTs) followed by a trustworthy FSM design algorithm and efficient vulnerability mitigation architecture (EVMA). Though our EVMA completely alleviates the vulnerabilities to STVFI and Trojan attacks, it slightly increases the overhead due to additional multiplexers. Hence, we also propose new secure FSM design algorithm and two new lightweight vulnerability mitigation architectures (LVMA-I and LIVMA-II) that control the FFs using existing clear and/or preset pins instead of multiplexers. The experimental results on AES and RSA encryption modules show that the proposed technique detects 100% VTs. Further, ASIC and FPGA implementation of the proposed LIVMA-II using Cadence RTL and Xilinx Vivado presents on an average 40%, 59.6%, and 51.1% reduced area, power and delay respectively compared to the well-known technique. Due to negligible design overhead, our technique is best suitable for designing secure controller of portable IoT devices.

A Design of Overlapped Chunked Code over Compute-and-Forward for Multi-Source Multi-Relay Networks.

This paper investigates the design of overlapped chunked codes (OCC) for multi-source multi-relay networks where a physical-layer network coding approach, compute-and-forward (CF) based on nested lattice codes (NLC), is applied for the simultaneous transmissions from the sources to the relays. This code is called OCC/CF. In this paper, OCC is applied before NLC before transmitting for each source. Random linear network coding is applied within each chunk. A decodability condition to design OCC/CF is provided. In addition, an OCC with a contiguously overlapping, but non-rounded-end fashion is employed for the design, which is done by using the probability distributions of the number of innovative codeword combinations and the probability distribution of the participation factor of each source to the codeword combinations received for a chunk transmission. An estimation is done to select an allocation, i.e., the number of innovative blocks per chunk and the number of blocks taken from the previous chunk for all sources, that is expected to provide the desired performance. From the numerical results, the design overhead of OCC/CF is low when the probability distribution of the participation factor of each source is dense at the chunk size for each source.

Exploring the Tradeoffs of Application-Specific Processing

Non-traditional processing schemes continue to grow in popularity as a means to achieve high performance with greater energy-efficiency. Data-centric processing is one such scheme that targets functional-specialization and memory bandwidth limitations, opening up small processors to wide memory IO. These functional-specific accelerators prove to be an essential component to achieve energy-efficiency and performance, but purely application-specific integrated circuit accelerators have expensive design overheads with limited reusability. We propose an architecture that combines existing processing schemes utilizing CGRAs for dynamic data path configuration as a means to add flexibility and reusability to data-centric acceleration. While flexibility adds a large energy overhead, performance can be regained through intelligent mappings to the CGRA for the functions of interest, while reusability can be gained through incrementally adding general purpose functionality to the processing elements. Building upon previous work accelerating sparse encoded neural networks, we present a CGRA architecture for mapping functional accelerators operating at 500 MHz in 32 nm. This architecture achieves a latency-per-function within $2{\times}$ of its function-specific counterparts with energy-per-operation increases between 21–188 $\times$ , and energy-per-area increases between 1.8–3.6 $\times$ .

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance

In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also induce single-event transients, initiated in the combinational logic and captured by the latches and flip-flops associated with the outputs of this logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error in logic functions already exist, but there are only few solutions allowing the correction, leading to a lot of hardware overhead in nonprocessor design. In this paper, we present a novel technique that includes several hardware architectures and an algorithm for their implementations, which reduces the cost of rollback in any kinds of circuit.

Optimizing DSP Cores Using Design Transformation [Hardware Matters

Reusable digital signal processing (DSP) intellectual property (IP) cores play a crucial role in numerous domains, including consumer electronics. However, optimizing DSP cores is crucial for the reduction of design area, delay, power, and so forth [1], [2]. Though several optimization techniques using evolutionary algorithms have been proposed, they incur design overhead and exploration time [1], [2].

An adaptive-resolution signal-specific ADC for sensor-interface applications

In this paper, a signal-specific analog-to-digital converter (ADC) with a new structure is proposed, in which the resolution of the ADC is adaptively adjusted by the activity of the input neural signal. The main advantages of the proposed technique for converting sparse and burst-like signals include (1) output data-rate reduction, and (2) power savings in ADC and its succeeding blocks. These benefits are obtained owing to the truncation of bits along in-active part of the signal. The extra blocks for realizing the proposed adaptive-variable resolution technique are fully-digital, which add minimum complexity and design overhead to the ADC. The proposed ADC has a suitable data compression capability at the expense of a tolerable degradation in quality of the reconstructed signal. The simulation results in a 180 nm CMOS technology show power savings of up to 39.5% and a compression ratio of 3.9?, as compared to the conventional structure.

Strong Stubborn Sets for Efficient Goal Recognition Design

Goal Recognition Design (GRD) is the task of redesigning environments (either physical or virtual) to allow efficient online goal recognition. In this work we formulate the redesign problem as an optimization problem, aiming at early goal recognition. To this end, we use a measure of worst case distinctiveness (wcd), which represents the maximal number of steps an agent may take before his goal is revealed. With the objective ofminimizing wcd, we construct a search space in which each node in the space is a goal recognition model (one of which is the original model given as input) and one can move from one model to another by applying a model modification, chosen from a set of allowed modifications given as input. Our specific contribution in this work includes the specification of a class of modifications for which we can prune the search space using strong stubborn sets. Such positioning allows reducing the computational overhead of design while preserving completeness. We show that the proposed modification class generalizes previous works in goal recognition design and enriches the state-of-the-art with new modifications for which strong stubborn set pruning is safe. We support our approach by an empirical evaluation that reveals the performance gain brought by the proposed pruning strategy in different goal recognition design settings.

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today’s very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

Improved Designs for All-Optical Adder Circuit Using Mach–Zehnder Interferometers (MZI) Based Optical Components

Since last decade, optical computing has emerged as one of the promising computing paradigm in the field of ultra-fast computations and the recent advancements of fabrication technology in photonic industry has further boosted research interests to investigate in this field. In this conjuncture, strategies for designing efficient optical circuits bear much significance toward building cost efficient logic circuits. Not only synthesis schemes but manual designs for logic components are found very effective in way to produce optimal designs. In this work, we present the optical domain designs of an important logic module of ALU—adder circuit. Not only we have made the adder circuit optical domain supporting one but also we have ensured that the designs are optimized too. Here we have worked with two types of adder circuits Carry-Lookahead Adder and Carry-Skip Adder. All the designs are made using Mach–Zehnder interferometers based optical components and interconnect. For both the adder types, two different designs are shown and in each of these designs both the circuit cost parameters and response time is improved. Design overhead and hardware complexities for all the circuits are computed and have compared with related work’s design, where we have found that our designs are having less delay and cost efficient compared to the existing ones.

Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines

The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption is more and more challenged by the shrinking technology. This paper redresses the weakest fork timing constraints for QDI asynchronous pipelines to work correctly under arbitrary wire and gate delay variability. We model a QDI circuit using the signal transition graph and propose a method to detect isochronic fork candidates. Extensive analysis is exploited to justify the necessary and sufficient isochronic fork selections of a QDI template. The proposed method works for many QDI templates, and it provides some necessary information about the constraint on any wire fork required for an asynchronous EDA tool in nanotechnology era. Experimental results demonstrate that the proposed method results in more robust QDI circuits in the expense of the least design overheads comparing to the similar method suggested in the current literature.