Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines

Abstract

The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption is more and more challenged by the shrinking technology. This paper redresses the weakest fork timing constraints for QDI asynchronous pipelines to work correctly under arbitrary wire and gate delay variability. We model a QDI circuit using the signal transition graph and propose a method to detect isochronic fork candidates. Extensive analysis is exploited to justify the necessary and sufficient isochronic fork selections of a QDI template. The proposed method works for many QDI templates, and it provides some necessary information about the constraint on any wire fork required for an asynchronous EDA tool in nanotechnology era. Experimental results demonstrate that the proposed method results in more robust QDI circuits in the expense of the least design overheads comparing to the similar method suggested in the current literature.