Robust Logic locking for Securing Reusable DSP Cores

Abstract

A System on Chip (SoC) used in Consumer Electronics (CE) systems integrates a number of reusable Intellectual Property (IP) cores from digital signal processing (DSP), multimedia etc. However, these DSP based IP cores are susceptible to various hardware threats such as piracy, Trojan insertion, overbuilding and reverse engineering. Thus, security of DSP cores is very crucial. An IP core can be secured against aforementioned hardware threats by employing logic locking based security mechanisms. This paper presents a novel robust logic locking using hybrid locking cells for securing DSP cores. The proposed logic locking is based on a novel advanced encryption standard (AES) based reconfigurable hybrid locking cell architecture that ensures strong security against key sensitization, removal and SAT attacks. The strength of the proposed approach has been assessed in terms of probability of obtaining correct key of a locked design in exhaustive trials. Results of proposed work on DSP cores yielded higher logic locking strength and lower design overhead compared to recent prior works.