Output Transconductance Research Articles

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (V t), drain current (I ON), OFF current (I OFF), and ON-OFF current ratio (I ON/I OFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (g m), output transconductance (g ds), gain (g m/g ds), transconductance generation factor (TGF), cut-off frequency (f T), maximum oscillation frequency (f max), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (g m2, g m3), voltage intercept points (VIP2, VIP3) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.

Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET

Device reliability issues originating from interface traps or bias temperature instability has been of great concern in emerging devices such as negative capacitance (NC)-fin field effect transistor (FinFET), gate-all-around field-effect transistor etc. Exploration of the interface traps at the different interfaces of these three-dimensional devices is of much importance in predicting the reliability of device behavior. In the proposed analysis, for the first time, we have demonstrated the individual and the overall impact of trap densities at the various practical interfaces present in the gate and spacer stack of the ferroelectric (FE)-dielectric spacer based NC-FinFET. The trap states in the proposed device alter the polarization dynamics and improve sub-threshold characteristics especially the off-state current (I OFF), thus revealing excellent short-channel characteristics. We have further evaluated the degree of performance degradation occurring due to interface traps by means of optimized capacitance matching (FE parameters), hysteretic window, output transconductance (gds) and voltage gain (AV ). Furthermore, we have also studied the impact of trap states on the mixed-mode characteristics of the spacer-based NC-FinFET inverter design.

New CMOS Linear Transconductors and their Applications

The object of this paper is to introduce a new CMOS differential input single output (DISO) transconductor (realizable from eight MOSFETs operating in saturation) and a dual input dual output (DIDO) transconductor (realizable with 16 MOSFETs operating in saturation) and their applications in realizing grounded/ floating, positive/ negative, electronically controllable resistors and inductors. The workability of all the prepositions has been demostrated by SPICE simulations using TSMC 0.18[Formula: see text] m CMOS technology parameters. The paper, thus, adds a number of useful electronically-controllable circuits to the existing repertoire of CMOS analog circuits for signal processing.

Over 10W/mm High Power Density AlGaN/GaN HEMTs With Small Gate Length by the Stepper Lithography for Ka-Band Applications

This study reports AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated by the Stepper Lithography on a 4-inch wafer for Ka-Band applications. Small gate length (LG) of 100 nm was achieved through a 2-Step Photolithography Process and the gate region of the AlGaN/GaN HEMT was defined by using two lithography steps to form gamma-shaped gates. The 4-inch AlGaN/GaN HEMT wafer demonstrated high electrical performance uniformity with respect to the maximum drain-source current density (IDSS), the peak extrinsic output transconductance (Gm), and the threshold voltage (Vth). At <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ DS}}\,\,=$ </tex-math></inline-formula> 20 V, the AlGaN/GaN HEMT exhibits an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ I}}_{\mathrm{ DSS}}$ </tex-math></inline-formula> of 1004.2 mA/mm, a Gm value of 363.6 mS/mm, a maximum output power density (POUT(MAX)) of over 10 W/mm, and a power gain of 8.8 dB with a maximum 51.1% Power-added efficiency (PAE) at 28 GHz in Continuous Wave (CW) mode. The results show the potential of AlGaN/GaN HEMT fabrication with high yield and outstanding RF performance using Stepper Lithography for 5G applications.

Investigation of dopingless transistor with field plates for analog and digital applications

This work demonstrates the influence of introducing field plates to an electrostatically doped JLT (DLT) to maximize the gate control over its channel and apparently to suppress the GIDL effects as well as L-BTBT and off-state tunneling current (IOFF). Therefore, the parasitic BJT action is minimized significantly in the device by the application of field plates, which in turn, minimizes the tunneling current (IOFF) and improves the (ION/IOFF) current ratio by at least 2 orders. The on-state performance of the device is also improved and is analyzed by improved analog parameters such as Transconductance Gm (26%), intrinsic gain AV (70%), Output transconductance GDS (25.8%), Early voltage VEA (40.6%) and Output resistance R0 (34.63%) in comparison to conventional DLT. We have given a simplified fabrication flow for the proposed device and performed the misalignment analysis for the device. Moreover, the circuit level analysis of the device is examined on H-SPICE using lookup table model in Verilog-A.

Simulation of Junctionless Transistor for Low Power Mix Circuit

Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

Temperature dependent analytical model for submicron GaAs-MESFET

MESFET are used in circuitsof gigahertz frequencies as they are based on gallium arsenide (GaAs) having electron mobility six times higher than that of silicon. An analytical model simulating different device current-voltage characteristics, i.e., output conductance and output transconductance of a 0.3μm gate MESFET with temperature dependence is proposed. The model is validated by comparing the results of the proposed model and those of the numerical simulation. The parameter values are computed using an intrinsic MESFET of two-dimensional geometry. In this work, the distribution of different output loads for varied applied voltages is considered. Simulation results obtainedunder temperature variation effectsfor load distribution and applied driven voltage variation are considered. The RMS and average errors between the different models and GaAs MESFET simulations are calculated to evidence the proposed model accuracy. This was demonstrated by a good agreement between the proposed model and the simulation results, which are found in good agreement. The simulation results obtained under temperature variations were discussed and found to complement those obtained in the literature. This clarifies the relevance of the suggested model analytical.

Equivalent Circuit Modeling of a Dual-Gate Graphene FET

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.

Emulation circuits of fractional-order memelements with multiple pinched points and their applications

Abstract This paper proposes voltage- and current-controlled universal memelements emulators. They are employed to realize the floating and grounded fractional-order memelements. The proposed emulators are implemented using different active blocks such as the second-generation current conveyor (CCII), Differential input double output transconductance amplifier (DOTA + ), balanced output CCII, and Differential voltage current conveyor (DVCC) with analog voltage multiplier. One of the main characteristics of the memristive elements is hysteresis loop behaviour with one pinched point, and the higher-order memelements have multiple pinched points. The higher fractional-order memductance (FOM) and inverse memductance (FOIM) emulators are proposed, which achieve multiple pinched-off points. The coordinates of the multiple pinched-off points and the conditions to achieve them are discussed in the I-V plane. Additionally, the effect of different orders α of the fractional-order capacitor (FOC) on the memelements characteristic is discussed. The circuit simulations for the proposed emulators have been verified using PSPICE simulations and validated experimentally at different orders. Finally, the grounded proposed emulator is employed in Chua's chaotic oscillator as an application presenting the effect of fractional-order on the chaotic response. Also, the floating proposed emulator is applied to a relaxation oscillator, to show the reliability of the proposed emulator.

Design and Analog Performance Analysis of Charge-Plasma Based Cylindrical GAA Silicon Nanowire Tunnel Field Effect Transistor

Due to the rigorous practice of scaling down the device technology, certain factors such as proper electrostatic controlling of the channel, dopingless substrate, and low thermal budget at the nanoscale are the keys to designing better, efficient and cost-effective semiconductor devices. In this paper, a Charge-Plasma (CP) based Gate-All-Around (GAA) Silicon Nanowire Tunnel Field Effect Transistor (NWTFET) is proposed. Charge-Plasma technique is used to induce electron and hole concentration within the drain/source regions respectively by depositing layers of metals with specific work functions. The RF and analog performance of Dopingless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (DL-GAA-NWTFET) are investigated and compared with Junctionless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (JL-GAA-NWTFET) and Conventional Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (C-GAA-NWTFET). The RF/Analog performance parameters such as Unity Gain Frequency (fT), Total Gate Capacitance (Cgg), Intrinsic Gain (Av), Early Voltage (VEA), Output Transconductance (gds), Transconductance to Gain Factor (TGF) and Transconductance (gm) are analyzed, which shows the enhanced output characteristics of the DL-GAA-NWTFET compared to JL-GAA-NWTFET and C-GAA-NWTFET. DL-GAA-NWTFET also provides two-order high ON-state current to the OFF-state current ratio (ION/IOFF) with an enhancement of the other sensing parameters.

High‐order realisation of MOSFET‐only band‐pass filters for RF applications

The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm2 and the power consumption is about 436 µW.

A novel algorithm to study the impact of the mismatch on analog building blocks: a case study in basic 35 nm CMOS amplifiers

In this paper, the context of modeling of the impact of mismatch and statistical variations on analogue circuit building blocks is emphasized. The aim is to develop a new algorithm which predicts the statistical behavior of important parameters of an amplifier including output resistance, voltage gain and trans-conductance. The relative error of standard deviation of statistical parameters will remain less than 5% compared with the most accurate Monte-Carlo (MC) simulations using atomistic library model-cards. In comparison with other models which are based on the normal distribution of parameters, the proposed model does not need this limiting presumption. On the other hand, the proposed algorithm is more efficient compared with time consuming MC atomistic simulations.

A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications

This paper presents a graded channel dual material gate junctionless transistor (GC-DMGJLT) for analog applications. We studied various performance parameters of GC-DMGJLT and compared them with uniform channel dual material gate junctionless transistor (UC-DMGJLT) using Sentaurus TCAD device simulator. The simulation results specify the superiority of GC-DMGJLT that yields higher values of drain current (Id), transconductance (gm) and cut-off frequency (ft) at the cost of slight increase in output transconductance (gds). Furthermore, besides DIBL all other short channel parameters are also suppressed in graded channel device resulting in its superiority over uniform channel device.

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance ( ${g}_{m}$ ), output transconductance ( ${g}_{\text {ds}}$ ), parasitic capacitances, device efficiency, cutoff frequency ( ${f}_{T}$ ), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients ( ${g}_{m1}$ , ${g}_{m2}$ , ${g}_{m3}$ ), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO2) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator.

Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET

Temperature is a thermal parameter which affects the device performance. This paper presents the impact of the temperature variation on the electrical characteristics such as tunneling width, subthreshold swing, threshold voltage, and ION/IOFF ratio of Ge/Si heterojunction Silicon on Insulator (SOI) Tunnel Field Effect Transistor (TFET) for different drain voltages. The device exhibits better performance in comparison with homojunction of the same device for different temperatures. This study reveals that OFF current of the device is independent of drain voltage variation irrespective of temperature variation. A small change in the subthreshold swing (SS) with temperature variation shows the weaker dependence of SS on temperature. The analog performance parameters such as transconductance, output transconductance, gate capacitance, and transconductance-to-drain-current ratio of the device are also examined. A small variation in analog parameters with temperature variation shows that the device could be used for the high-temperature analog circuit applications. A broad range of temperature from 200 K to 400 K has been used to analyze the performance of the device using Synopsys Technology Computer Aided Design (TCAD) simulation tool.

A new CMOS ZC-CDTA realization and its filter applications

The Z copy current differencing transconductance amplifier (ZC-CDTA) is a new current-mode active element that was introduced recently. ZC-CDTA is improved from the current differencing transconductance amplifier (CDTA) and has increased its universality. In the current study, a CMOS implementation of ZC-CDTA is proposed. The first stage of ZC-CDTA consists of a current differencing unit. The output stage consists of a dual output transconductance amplifier. Furthermore, a third-generation current conveyor is used to copy the Z terminal current instead of a classical current mirror. A fourth-order filter application employing ZC-CDTAs is given and simulation results are added. The ZC-CDTA-based filter is designed starting from a previous filter structure that employed conventional CDTAs. Thanks to the Z copy, the high-pass filter output problem is solved for the conventional CDTA filter structure. AMS 0.18-$\mu $m CMOS parameters are used for the simulations.

Influence of gate-to-source and gate-to-drain recesses on GaAs camel-like gate field-effect transistors

In this article, the characteristics of the GaAs homojunction camel-like gate field-effect transistors with and without the gate-to-source and gate-to-drain recesses structures are first investigated and compared. As to the device without the recesses structure, a second channel within the n+-GaAs cap layer is formed at large gate bias, which could enhance the drain output current and transconductance. Furthermore, a two-stage relationship between drain current (and transconductance) versus gate voltage is observed in the recesses structure. The simulated results exhibit a maximum drain saturation current of 447 (351 mA/mm) and a maximum transconductance of 525 (148 mS/mm) in the studied device without (with) the recesses structure. Consequentially, the demonstration and comparison of the variable structures provide a promise for design in circuit applications.

Pulsed I-V Auto-Measurement of High Power MOSFETs without Self-Heating

A novel Sagittarius automatic Pulsed I-V measurement system was developed. This new system eliminated the self-heating effect which affected static measurements of High Power MOSFETs using conventional methods. It provided the true output conductance and trans-conductance, solved the device modeling problems caused by negative output conductance of high power devices. The automation measurement function can fulfill the mass measurement requirements of semiconductor industry with high efficiency and accuracy.

PATHOLOGICAL REALIZATIONS OF BOTA AND FDDTA USING GROUNDED RESISTORS

Sixteen pathological realizations of the balanced output transconductance amplifier (BOTA) using four grounded G are generated. Each of these circuits is realizable using four current conveyors (CCII) or four inverting current conveyors (ICCII) or a combination of four CCII and ICCII. Six new pathological realizations of the BOTA using two grounded G based on current subtraction are introduced. Four new pathological realizations of the BOTA using two grounded G based on voltage subtraction are introduced. Several new pathological realizations of the FDDTA as a voltage subtraction stage and a BOTA stage are also given. Simulation results are included.

GENERATION OF THE MINIMUM COMPONENT OSCILLATORS FROM SALLEN KEY FILTERS

Two new minimum passive component oscillators using inverting current conveyor (ICCII–) acting as a voltage negative impedance converter are generated from the Sallen Key low-pass and high-pass filters. It is also shown that the Sallen Key low-pass, high-pass, and band-pass filters are the origin of the three minimum component oscillators using the current conveyor acting as a current negative impedance converter. In addition, it is also shown that the Sallen Key high-pass and band-pass filters are the origin of the two minimum component oscillators using single input single output transconductance amplifier as the active element. Although this paper is considered partially a review paper it includes new generation methods and new minimum component oscillator circuit realizations. Simulation results for the new oscillators using ICCII– are included.