Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET

Abstract

Device reliability issues originating from interface traps or bias temperature instability has been of great concern in emerging devices such as negative capacitance (NC)-fin field effect transistor (FinFET), gate-all-around field-effect transistor etc. Exploration of the interface traps at the different interfaces of these three-dimensional devices is of much importance in predicting the reliability of device behavior. In the proposed analysis, for the first time, we have demonstrated the individual and the overall impact of trap densities at the various practical interfaces present in the gate and spacer stack of the ferroelectric (FE)-dielectric spacer based NC-FinFET. The trap states in the proposed device alter the polarization dynamics and improve sub-threshold characteristics especially the off-state current (I OFF), thus revealing excellent short-channel characteristics. We have further evaluated the degree of performance degradation occurring due to interface traps by means of optimized capacitance matching (FE parameters), hysteretic window, output transconductance (gds) and voltage gain (AV ). Furthermore, we have also studied the impact of trap states on the mixed-mode characteristics of the spacer-based NC-FinFET inverter design.