Abstract
This work demonstrates the influence of introducing field plates to an electrostatically doped JLT (DLT) to maximize the gate control over its channel and apparently to suppress the GIDL effects as well as L-BTBT and off-state tunneling current (IOFF). Therefore, the parasitic BJT action is minimized significantly in the device by the application of field plates, which in turn, minimizes the tunneling current (IOFF) and improves the (ION/IOFF) current ratio by at least 2 orders. The on-state performance of the device is also improved and is analyzed by improved analog parameters such as Transconductance Gm (26%), intrinsic gain AV (70%), Output transconductance GDS (25.8%), Early voltage VEA (40.6%) and Output resistance R0 (34.63%) in comparison to conventional DLT. We have given a simplified fabrication flow for the proposed device and performed the misalignment analysis for the device. Moreover, the circuit level analysis of the device is examined on H-SPICE using lookup table model in Verilog-A.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
