Phase Detector Output Research Articles

A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

Antenna System for Trilateral Drone Precise Vertical Landing

This paper presents a radio frequency system that can be used to perform precise vertical landings of drones. The system is based on the three-way phase shift detection of a signal transmitted from the landing point. The antenna system is designed by taking into account parameters such as landing tracking area, analog to digital converter (ADC) resolution, phase detector output range, antenna polarization and the effect of antenna axial ratio. The fabricated prototype consists of a landing point antenna that transmits a signal at 2.46 GHz, as well as a drone tri-antenna system that includes a phase shift detection circuitry, ADC and a simple control program that provides the correction instructions for landing. The prototype provides an averaged output data rate (ODR) suitable for landing maneuvers (>300 Hz). A simple system calibration procedure (detector output zeroing) is performed by aligning the antenna system. The measurements performed at different altitudes demonstrate both the correct operation of the proposed solution and its viability as an instrument for precision vertical landings.

Nonlinear reverberation spectroscopy with phase-sensitive superheterodyne reception

A technique is presented for determining elastic nonlinearity of materials from resonant frequency shifts as a function of signal amplitude during free vibrational decay after tone-burst excitation. The technique differs from previous nonlinear reverberation spectroscopy (NRS) techniques in that it employs phase-sensitive superheterodyne reception. Time-dependent amplitudes of in-phase and out-of-phase components of signals, relative to a reference sinusoid at the excitation frequency, are provided through analog hardware processing in the absence of digitization of the signal from the vibrational sensor. The time-dependent phase and amplitude of the signal are determined through software analysis of these in-phase and out-of-phase components, and the instantaneous frequency during free decay is then determined from the time derivative of the phase. With this approach, superheterodyne reception and low-pass filtering of the phase-detector outputs lead to a great reduction in noise and computation effort, relative to direct digitization and software processing of the sensor signal, while retaining information on frequency shifts on a relevant time scale during ringdown. As with other NRS techniques, rapid acquisition of data on amplitude dependence of the resonant frequency during ringdown leads to minimization of systematic errors from temperature drift. The technique is demonstrated with noncontacting electromagnetic-acoustic transduction on custom alloyed Al (0.2 at.% Zn) and commercial Al 7075 cylinders with axial-shear resonant frequencies between 658 kHz and 659 kHz. The precision of measurements of relative frequency shifts is found to be on the order of 0.1 parts per million (ppm), exceeding by two orders of magnitude the best reported precision of nonlinear resonant ultrasound spectroscopy (NRUS).

Додаткова радіолокаційна ознака для розпізнавання надводних об’єктів

Subject and Purpose. The article is devoted to the radio recognition of moving waterborne objects (sea-going ships). The problem lies in the lack of radar signatures, which is especially true for coherent radar in continuous mode, implying that more signatures for the waterborne object recognition is highly needed. An additional signature can be gained just by means of a simple mathematical processing of target reflection signals. This is particularly important for radio recognition systems in current use because this will hardly complicate the system structure. Hence, it will not affect its cost either. Methods and Methodology. The method developed for the retrieval of an additional radar signature characteristic of waterborne objects moving across a rough sea surface is based on a simple mathematical processing of a signal reflected from the moving waterborne object and taken from the phase output of coherent radar. The method approbation is by the mathematical modeling of signals at the phase detector output in the event of three waterborne objects such that have identical scattering cross sections but different periods of the side and keel vibrations. Results. Based on the mathematical modeling results, it has been shown that each of the local scattering centers keeps the ratio of the linear speeds of side and keel vibrations approximately the same for the same object. But the employed ratio takes different values for different objects. Conclusion. Having a single standard coherent radar in continuous mode and guided by the developed methodology, one can gain an additional signature for the target recognition, which is a ratio of the linear speeds of side and keel vibrations of the target. The suggested methodology can be used for the radio recognition of waterborne objects moving across a rough sea surface.

A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.

Modified FMCW system for non-contact sensing of human respiration

Small displacement detection capability becomes an important key for developing non-contact sensor for human respiration based on radar system. Frequency modulated continuous wave (FMCW) radar has been widely studied and applied for many applications. With respect to the conventional perspective, large bandwidth is needed for detecting the small displacement related to the human respiration. Meanwhile, extracting the respiration pattern from Doppler response has a drawback in identifying the small displacement location. In this paper, the modification on FMCW system was proposed for obtaining the capability in detecting the human respiration and its distance from the radar. Detecting the phase value of the low pass filter (LPF), output from conventional FMCW was investigated and applied as a modification concept. The pattern, rate and amplitude of respiration are extracted from phase detector output. Beat frequency detection is still elaborated for synthesising the reference signal for phase detection. The result shows that the modified FMCW system proposed the capability of detecting the rate and amplitude respiration and location of the target.

Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal–Oxide–Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network‐Based Stochastic Learning

Herein, a robust programmable stochastic weight generation method for a memristive neural network is proposed. There have been few prior algorithm suggestions for crossbar neural network‐based stochastic learning; however, there has not been much attention focussed on robust physical implementations. As a result, coming up with a robust method to provide the probability generator is an essential knob for its physical implementation. Here, implanting such stochastic behavior into the weight update signal itself is proposed, by multiplying it with the randomized probability sequence. To generate such probability sequence, bang‐bang dithering of a phase‐locked loop (PLL) with a binary phase detector (PD) is used. The programmable probability is enabled by introducing an offset for the PD outputs. Yet the dithering sequence has deterministic nature, phase noise of complementary metal–oxide–semiconductor (CMOS) ring oscillator to randomize the deterministic dithering is exploited. As a result, this lower power oscillator offers a better probability sequence, which enables an ultralow power circuit implementation.

A Fully Digital Semirotational Frequency Detection Algorithm for Bang–Bang CDRs

This brief presents a new frequency acquisition method using a semirotational frequency detection (SRFD) algorithm for referenceless clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the bang–bang phase detector (BBPD) outputs to estimate the current phase state and detects the frequency mismatch between the input data and the sampling clock. The voltage-controlled oscillator (VCO)-track path in a digital loop filter (DLF) enables online calibration of a drifted frequency of the VCO caused by temperature or voltage variation after a frequency acquisition. The proposed algorithm can be implemented as a digitally synthesized circuit, lowering design efforts for referenceless CDRs. A 10-Gb/s transceiver IC with the proposed algorithm, fabricated in a 65-nm CMOS process, demonstrates successful recovery of the input phase without any reference clock.

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm CMOS. The technique increases the CDR’s loop gain to suppress the most jitter while monitoring the autocorrelation function of the bang-bang phase detector (BB-PD) output to prevent the CDR from becoming too underdamped. The proposed technique requires no knowledge of the CDR’s loop latency or input jitter characteristics.

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR

We present a technique to measure random jitter in a phase interpolator (PI)-based clock and data recovery (CDR) circuit by injecting a controlled amount of square-wave jitter into its edge clock and monitoring its effect on the autocorrelation function of the CDR’s bang-bang phase detector output. Jitter is injected by adjusting the code of the edge PI while the autocorrelation function is measured by on-chip counters. Since the injected jitter only affects the edge clock, the CDR remains operational during jitter injection. Using this technique, the rms relative jitter between the clock and data at the CDR input can be estimated with sub-picosecond accuracy as demonstrated in measurements of a 28 Gb/s half-rate digital CDR fabricated in 28 nm CMOS.

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of $\pi $ /4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The stand-alone ILRO demonstrates 0.2–11.7 GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and −40 °C to +120 °C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7-bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2–11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

PLL for Grid Synchronization of Single Phase Distributed Generation System

This paper presents the implementation of an adaptive phase locked loop (EPLL) technique for grid synchronization of single phase distributed generation system(DGS) using a low cost microcontroller. The adaptive PLL consists of a quadrature signal generator(QSG) based on a second order generalized integrator(SOGI) , Parks transform, low pass filter(LF) and frequency phase shift generator(FPG). The QSG- SOGI works as an adaptive notch filter and used for cancellation of harmonic components in the grid voltage. The QSG-SOGI and Parks Transform system is used for enhancing the performance of conventional multiplier based phase detector (PD). The required information about amplitude and phase of grid voltage is extracted from the vd and vq component of PD output. The objective of this paper is to implement the EPLL using a low cost microcontroller for accurate estimation the grid parameters like phase, frequency and voltage amplitude. The experimental results of implementation are discussed in the paper.

An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase-locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented. By sensing the supply noise using an analog-to-digital converter (ADC), an observer–controller loop filter jointly processes the ADC and phase detector outputs to determine the oscillator control signals that minimize the output jitter. The proposed digital PLL is shown to be significantly more robust to supply noise compared with a conventional PLL.

A 28 GHz SiGe PLL for an 81–86 GHz E-band beam steering transmitter and an I/Q phase imbalance detection and compensation circuit

This paper presents two circuits, a complete 1.5 V 28 GHz SiGe beam steering PLL and a standalone 28 GHz QVCO with I/Q phase imbalance detection and compensation. The circuits were designed in a SiGe process with fT = 200 GHz. The PLL is intended to be used for beam steering in an 81---86 GHz E-band transmitter. Phase control is implemented by DC current injection at the output of a Gilbert architecture phase detector showing a simulated phase control sensitivity of 1.2°/µA over a range close to 180°. The simulations use layout parasitics for the QVCO, frequency divider, and phase detector, and an electromagnetic model for the QVCO inductors. The divider is implemented with four cascaded divide-by-two current-mode-logic blocks for a reference frequency of 1.75 GHz. For closed loop simulations of PLL noise and stability, the QVCO is represented with a behavior model with added phase noise. This simulation technique enabled faster simulation time of the PLL. The PLL in band phase noise at 1 MHz offset equals ?115 dBc/Hz. Excluding output buffers, the entire PLL consumes 52 mW plus a minimum 7 mW from a variable high voltage supply required to extend the PLL locking range. The measured phase noise of the standalone QVCO equals ?100 dBc/Hz at 1 MHz offset. Since E-band radio links utilize higher order QAM modulation, the bit-error rate is sensitive to I/Q phase error. In the measured standalone QVCO with I/Q phase imbalance detection and compensation, the error is detected in two cross coupled active mixers that have an output DC level proportional to the phase error. The error can then be eliminated adjusting the bias of four varactors connected to the QVCO outputs. The current consumption of the chip equals 14 mA from a 1.5 V supply and 57 mA from a 2.5 V supply dedicated to the detector and 28 GHz output measurement buffers.

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps.

A novel DSP‐based PFC‐DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity

SummaryThis paper proposes a new digital signal processing (DSP)‐based phase frequency controlled digital phase locked loop. Here, a very simplistic form of fuzzy logic controller with the help of carrier phase and frequency error as input data is used to provide an acquisition aid. A frequency discriminator is employed to generate frequency error, and phase detector output is taken for phase error. This addition of an acquisition aid helps the loop to achieve the minimum acquisition time and maximum noise rejection simultaneously. An additional phase control in the digitally controlled oscillator makes the loop perform even better towards this goal. The implementation of the proposed loop is carried out on a reconfigurable logic platform using System Generator®;, a tool from Xilinx®; used to design real‐time DSP application. A significant improvement of time domain characteristics are observed as well as the performance in presence of additive white Gaussian noise is demonstrated in terms of the reduction in steady‐state phase jitter and enhancement in output signal to noise ratio in the proposed loop. Copyright © 2014 John Wiley & Sons, Ltd.

A Motor Speed Servo System Based on the Dual Loop PLL

PLL-MSC (Phase Locked Loop Motor Speed Control) systems can completely reject speed error and steady-state phase error for constant-speed input signals. However, it is not usually applied to systems with inputs including acceleration, because they have poor tracking speed and strange pull-in behavior.In the field of radio communication, “dual-loop PLL” is very effective for such signals. It can not only enable high-speed tracking, but also cancel phase error.In the digital implementation of the PLL-MSC, it can achive easily by inserting loop filters into both feed back paths, and employed a special adder in PWM to implement loop addition for the two phase detector outputs. The scheme was implemented by programming an FPGA, and satisfiable results were obtained.

Phase Spectrum of Signals in Ground-Penetrating Radar Applications

The phase structure of ground-penetrating radar (GPR) signals operating on the basis of a stepped-frequency continuous wave (SFCW) is extracted to obtain additional information about the physical properties of buried objects. The phase structure is obtained from a signal-phase-frequency spectrum by applying the discrete Fourier transform to signals on the output of an SFCW georadar quadrature phase detector. We show that the phase gradient of a phase-frequency spectrum of signals reflected from underground layers and buried objects is determined by their electrical properties. We represent a signal phase structure during the georadar movement along the ground surface as an image of phase isolines (lines corresponding to the phase shift of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> 2¿). We show that the spatial variability of isolines is determined by a medium physical property change or by the presence of inhomogeneous objects.

GNSS 신호를 이용한 회전체의 롤 회전 속도 추정 기법

This paper proposes a roll rate estimation method for spinning vehicles. The carrier phase and frequency variations caused by spinning of vehicles are observed and the roll rate estimator is designed on the observation. The roll rate estimator consists of phase detector and zero crossing counter. The phase detector computes phase variation using in-phase and quadrature value from the correlator. By using zero crossing counter, the roll rate can be estimated since the output of phase detector is changed in proportion to the roll rate. Experiment a results show that estimated roll rate error is smaller than 0.0578Hz.

Improved phase detector for electro-optical phase-locked loops

A phase detector with a reduced spurious output has been realised. Since spurious products at the output of a phase detector in an electro-optical phase-locked loop (PLL) can hardly be filtered out, this kind of a phase detector is recommended for such an application. The parallel operation of two conventional phase detectors (double-balanced mixers or fast-logic EXOR gates) is presented theoretically and then verified with a practical experiment. Maintaining a phase shift of 90° between the two phase detectors, the spurious output at twice the comparing frequency can be reduced significantly, resulting in a much cleaner output spectrum of the electro-optical PLL synthesiser.