A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator

Abstract

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.