Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Abstract

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm CMOS. The technique increases the CDR’s loop gain to suppress the most jitter while monitoring the autocorrelation function of the bang-bang phase detector (BB-PD) output to prevent the CDR from becoming too underdamped. The proposed technique requires no knowledge of the CDR’s loop latency or input jitter characteristics.