A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Abstract

A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.