Abstract
The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.
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