A novel approach to analysis and design of bang-bang CDR circuits

Abstract

Purpose – Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues. Design/methodology/approach – The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking). Findings – In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-μm CMOS process. Simulation results show that good conformance between analytical equations and simulation results. Originality/value – The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.