Output-capacitorless Low-dropout Regulator Research Articles

A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management

This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper, an NMOS output-capacitorless low-dropout regulator (OCL-LDO) featuring dual-loop regulation has been proposed, achieving fast transient response with low power consumption. An event-driven charge pump (CP) loop with the dynamic strength control (DSC), is proposed in this paper, which overcomes trade-offs inherent in conventional structures. The presented design addresses and resolves the large signal stability issue, which has been previously overlooked in the event-driven charge pump structure. This breakthrough allows for the full exploitation of the charge-pump structure's potential, particularly in enhancing transient recovery. Moreover, a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage, leading to favorable static characteristics. A prototype chip has been fabricated in 65 nm CMOS technology. The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current (I Q) and can recover within 30 ns under 200 mA/10 ns loading change.

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

A Low-Power, Fast-Transient FVF-Based Output-Capacitorless LDO with Push–Pull Buffer and Adaptive Resistance Unit

An output-capacitorless low-dropout regulator (LDO) with a push–pull buffer was presented in this paper. The proposed push–pull buffer was able to provide a large charge and discharge current to increase the slew rate at the gate of the power transistor effectively, thereby improving the transient response of this LDO. In addition, an adaptive resistance unit (ARU) was proposed to solve the right half-plane zero problem caused by Miller compensation to optimize the loop stability of the LDO. The proposed LDO was implemented in a 0.18-µm CMOS technology. Simulation results showed that the quiescent current of this LDO was only 16.1 µA. It regulated the output at 1.5 V from a 1.8 V supply, with a dropout voltage of 300 mV at the maximum output current of 50 mA. The maximum value of the voltage spike was 129 mV. Additionally, the recovery time of the LDO was 0.2 µs.

A fast transient FVF-based output capacitorless LDO with self-feedback biasing

An improved flipped voltage follower (FVF) based output-capacitorless low-dropout regulator (OCL-LDO) with self-feedback biasing has been proposed in this paper, achieving better performance without increasing the number of transistors or adding complicated circuits for the customized transient performance. With the proposed self-feedback biasing technique, the equivalent transconductance of the error amplifier is boosted effectively, so that the DC gain of the proposed FVF-LDO is increased and thus both the load and line regulations are improved. At the same time, the dynamic bias current is generated to enhance the transient response. In addition, a single-transistor-based fast discharge loop is added to further enhance the transient response. The proposed OCL-LDO has been designed and fabricated in 180-nm CMOS technology. The chip area is 0.017 mm2, and the measured quiescent current is 79 μA. The proposed LDO can be stable with 0 ∼ 100-pF output capacitance under current ranges from 0 ∼ 100 mA, and the FoM is as small as 0.0036 ps when loading current changes from 0 to 100 mA.

An Output-Capacitorless Low-Dropout Regulator with Slew-Rate Enhancement.

A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power transistor when a large voltage spike at the output is detected. In addition, a feed-forward transconductance cell is introduced to form a push–pull output structure with the power transistor. The simulation results show that the maximum transient output voltage variation is when the load current is stepped from to in with a load capacitance of , and the settling time is . The proposed OCL-LDO consumes a quiescent current of and has a dropout voltage of for the maximum output current of .

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks to the combined indirect-direct nested Miller compensation which ensures stability and maintains a high loop gain over the whole range of load condition. Fabricated in a 0.18-μm CMOS process and consuming 14 μA of quiescent current, the OCL-LDO, while supplying the load current between 0 mA to 100 mA, is capable of driving the load capacitance in the range of 0-1 nF; with a minimum load current of 1 mA, however, the OCL-LDO can drive up to 10 nF of load capacitance. Over such wide load-current and load-capacitance ranges, the OCL-LDO achieves DC load and line regulations of 0.025 mV/mA and 0.5 mV/V, respectively.

A Transient-Enhanced Output-Capacitorless LDO With Fast Local Loop and Overshoot Detection

An output-capacitorless low-dropout regulator (OCL-LDO) with simple structure and fast transient response is proposed for system-on-chip (SoC) applications. A super source follower is inserted into a cascoded flipped voltage follower to drive the power transistor, which forms a fast-local loop for quick turn-on. A robust overshoot detection circuit consuming only leakage current is proposed for fast turn-off. The combination of these two techniques significantly reduce the overshoot/undershoot voltages and achieve fast settling time during load steps. A simple yet effective additional turn-around stage is added in the error amplifier to improve the positive phase slew rate for potential dynamic voltage scaling (DVS) function in battery-operated systems. The LDO is implemented in a 65 nm CMOS process and it can deliver a 20 mA load current with 0.9 V regulated output and 150 mV dropout voltage. It occupies an active area of 0.01 mm $^{\mathbf {2}}$ and can work stably in a load range from 0 to 20 mA with $65~\mu \text{A}$ quiescent current. The measured results show a settling time about 100 ns for load steps from $100~\mu $ A to 20 mA as well as V $_{\mathbf {REF}}$ and V $_{\mathbf {IN}}$ steps.

A voltage-adjustable output-capacitorless LDO regulator with split-length current mirror compensation and overshoot/undershoot reduction

An output-capacitorless low-dropout regulator (OCL-LDO) using split-length current mirror compensation and overshoot/undershoot reduction circuit are presented in this paper. At a supply of 1.5 V and a quiescent current of 8.2 µA, the proposed scheme can support a maximum load current of 50 mA. The proposed OCL-LDO has a range of output voltage from 0.8 to 1.25 V with 1.5 V supply. The proposed regulator is designed and post-simulated by UMC 55-nm standard CMOS process. The simulation results show that the proposed scheme is stable in different temperatures and process corners with 10 pF output capacitor. The maximum value of overshoot and undershoot is 69.0 mV and 91.5 mV, respectively.

A 65nm 0.6–1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback

This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC). Proposed dynamic amplifier based VDTC allows low voltage operation and significantly reduces the quiescent current. The linear characteristics of VDTC result in output ripple-less operation and good regulation performance. Using direct output feedback through a small coupling capacitor, the gate voltage of the power transistor is instantly compensated to mitigate fluctuation of the output voltage when a sharp load transient occurs. Fabricated in 65 nm LP CMOS, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6-1.2 V and a load current of over 30 mA across all voltages without an output capacitor. With reduced output impedance due to direct output feedback, the measured undershoot is 158 mV, which is recovered in 9.6 μs, when the load current changes by 28 mA in 1 ns. The peak current efficiency is more than 99.99% and the figure of merit (FOM) is 0.202 fs. The active area of the control block is 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.58-to-0.9-V Input 0.53-V Output 2.4-$\mu$ W Current-Feedback Low-Dropout Regulator With 99.8% Current Efficiency

This letter presents an output capacitor-less low-dropout regulator (LDO) topology that can operate from 0.58-to-0.9-V supply, and has a minimum dropout voltage of 50 mV. Compared with traditional analog LDOs, the proposed design incorporates a current reference into the regulator loop and uses current feedback to alleviate the design constraints caused by the limited voltage headroom. The LDO is implemented in a 0.13- $\mu \text{m}$ standard-threshold-voltage CMOS process. Measurement results show that depending on the supply voltage the quiescent power consumption is from 2.4 to 3.6 $\mu \text{W}$ , and the current efficiency is 99.8%. The mean value of the output voltage of 16 samples is 0.53 V and the standard deviation is around 4 mV. The load current range of the proposed LDO is from 0 to 3 mA, and it is capable of driving a load capacitor of up to 120 pF.

Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

Dual active capacitive feedbacks for output capacitor-less low-dropout regulator

An output capacitor-less low-dropout (OCL-LDO) voltage regulator with dual active feedback paths is presented in this paper. The dual active feedbacks provide frequency compensation and spike voltage suppression. Two feedback loops are formed by capacitors Cc and Ca, respectively. The capacitor Ca path detects output voltage to suppress undershoot and overshoot during load transient. The frequency compensation is achieved by capacitor Cc, which helps the LDO regulator not only improve stability, but also enhance transient response without large current consumption. The total utilized capacitance values are only 1.5 pF. The proposed OCL-LDO was fabricated in 0.18 μm CMOS technology with supply voltage of 1.8 V. The LDO consumes 21 μA of quiescent current and the chip area is 0.47 mm × 0.49 mm. The measured output voltage difference is 90 mV when the load current is increased from 50 μA to 100 mA with CL= 100 pF and recovery time less than 1 μs. The power supply rejection is − 51.7 dB at 1 kHz.

Dynamic current-boosting based FVF for output-capacitor-less LDO regulator

A flipped voltage follower structure based on a dynamic current boosting technique is proposed which enables the fast-transient behavior. It is applied to an output capacitor-less low-dropout (LDO) regulator to improve the output transient response and reduce the over/undershoots of the output voltage when the load current or the input voltage is suddenly changed. The proposed low-dropout regulator is simulated in 0.18 μm CMOS technology, which the output voltage is regulated at 1 V with a dropout voltage of about 114 mV. The output voltage over/undershoot amplitudes of the proposed LDO are obtained in 99.52/551.8 mV with the settling time of fewer than 1.3 μs for the load current changes from 0.1 to 100 mA with 200 ns rise/fall times.

A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0–100-mA Load Current Range

An ultralow quiescent current output-capacitorless low-dropout (LDO) regulator dedicated to Internet-of-Things applications is presented. This is based on an improved adaptive-stage adaptively biased architecture together with the novel frequency compensation to achieve the good stability and fast transient response under ultralow bias current. Validated by the CMOS 0.18- $\mu \text{m}$ technology, the chip area is 0.055 mm2. The proposed LDO regulator consumes only 407-nA quiescent current at no-load current while providing a 1-V output with a maximum load current of 100 mA from a 1.2-V power supply. The adaptive frequency compensation is presented, including a new transistor degeneration frequency compensation (TDFC) to sustain the stability at ultralow quiescent bias. Besides, it also includes Q-reduction and Miller-RC compensation schemes to ensure the stability for full load current range. In addition, a substantial improved transient response is obtained by the proposed distributed overshoot reduction circuit together with the TDFC scheme and the adaptively feed-forward biasing topology. The measured results have shown that the undershoot/overshoot voltage is 117 mV/35.33 mV and the output can settle in $1.56~\mu \text{s}$ with 1% accuracy. Compared to fixed-biased and adaptively biased architectures, it shows the lowest value in figure of merit (FOM) at the quiescent state. Compared to adaptively biased architectures, it shows the improved FOM at the maximum quiescent state.

A fast transient response and high current efficiency output-capacitorless low dropout regulator for low-power SoC applications

This paper presents an output capacitor-less low-dropout regulator (LDO) with a fast transient response and high current efficiency. The proposed slew rate enhancement circuit is activated only when the output voltage is instantaneously changed due to the transient of the load current. This method cannot only instantaneously increase the bias current source current for rapid output voltage recovery in order to enhance the load regulation but also reduce power consumption. The proposed LDO was fabricated using the standard 0.18 μm CMOS process. Measurement results revealed that the proposed LDO can operate from 1.2 to 1.8 V at an output voltage of 1 V and can provide loading current ranging from 3 to 100 mA. The current efficiency of the LDO was determined to be 99.96% at the maximal load current of 100 mA.

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.